141results about How to "Increase parasitic capacitance" patented technology

A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.

The invention relates to an array substrate, a display screen and a display device. The array substrate comprises a substrate body, at least one first switch transistor and at least one second switchtransistor, a corresponding display area on the substrate body comprises pixels in array distribution and is divided into a special-shaped display area and a non-special-shaped display area, the number of the pixels in each row of the special-shaped display area is smaller than that in any row of the non-special-shaped display area, the first switch transistors are positioned in the special-shapeddisplay area and correspond to the pin the special-shaped display area, and the second switch transistors are positioned in the non-special-shaped display area and correspond to the pixels in the non-special-shaped display area; width-length ratio of the first switch transistors is equal to that of the second switch transistor, and grid area of the first switch transistors is greater than that ofthe second switch transistors. The technical problem that displayed images are nonuniform in brightness caused by load difference in the special-shaped display area and the non-special-shaped displayarea is solved, and display effect is improved.

A semiconductor device and a method of forming the semiconductor device are provided. The semiconductor device may include, but is not limited to, a semiconductor substrate and a third array of semiconductor elements. The semiconductor substrate may include a first array of separate grooves, a second array of separate active regions, and at least an isolating region, the isolating region separating the separate active regions from each other. Each separate groove extends in the separate active region and does not extend over the isolating region. The third array of semiconductor elements is provided on the semiconductor substrate. Each of the semiconductor elements has an electrically conductive portion that is provided in the separate groove. The semiconductor element may be a trench gate transistor, and the electrically conductive portion may be a gate electrode.

An embodiment of the invention provides a COA (color filter on array) substrate, a production method thereof and a display device and relates to the technical field of display. By the aid of the COA substrate, the production method thereof and the display device, the problem that large parasitic capacitance can be generated between a common electrode and a grid line and / or between the common electrode and a data line in the prior art is solved, signal delay is avoided, normal transmission of signals is guaranteed, and the display quality of pictures of the display device is improved. The COA substrate comprises a grid line, a data line, a common electrode layer and a black matrix, wherein the black matrix is arranged between the grid line and the common electrode layer and / or between the data line and the common electrode layer and is made of metal materials. The COA substrate, the production method thereof and the display device are applied to the display device production technology.

The invention discloses a display panel and a display device, and belongs to the technical field of display. The display panel comprises a display area, wherein the display area includes a plurality of data lines and a plurality of pixel electrode; first sub-pixels and second sub-pixels in the display area are alternately arranged to form pixel rows, one pixel row is driven by a first scanning line and a second scanning line together, and the time when a scanning signal is inputted into the first scanning line and the time when a scanning signal is inputted into the second scanning line are overlapped when the first scanning line and the second scanning line drive the same pixel row; each sub-pixel includes a pixel electrode; each first sub-pixel includes a first transistor, and each second sub-pixel includes a second transistor; the parasitic capacitance between a source electrode and a grid electrode in the first transistor is the first parasitic capacitance, the parasitic capacitance between a source electrode and a grid electrode in the second transistor is the second parasitic capacitance, and the second parasitic capacitance is greater than the first parasitic capacitance. The display panel can ensure that the brightness of the second sub-pixels and the brightness of the first sub-pixels tend to be the same and improve the display uniformity.

An improved analog switch for use in an ultrasound elastography probe is disclosed. The improved analog switch results in less heat dissipation compared to prior art analog switches.

Provided is an organic EL display apparatus in which, depending on a situation in which a user uses the organic EL display apparatus, display with high light use efficiency and high front luminance (luminous efficiency)or display with large view angle is selectable. Pixels each include subpixels having different optical characteristics from each other, and the pixels and the subpixels are respectively arranged in a staggered pattern. Further, the subpixels are independently controlled.

The invention provides an interconnection line structure and a forming method of the interconnection line structure. The forming method of the interconnection line structure comprises the following steps of: providing a semiconductor substrate, wherein a semiconductor device is formed in the semiconductor substrate; forming an interlayer medium layer on the semiconductor substrate; forming a conductive layer on the interlayer medium layer; after the conductive layer is formed, forming grooves in the conductive layer and the interlayer medium layer, wherein the depth of the grooves is less than a thickness sum of the conductive layer and the interlayer medium layer, and a depth-to-width ratio of the grooves is more than 0.8; after the grooves are formed, depositing intermetallic medium layers, covering the conductive layer and filling the grooves through the intermetallic medium layers, and forming air gaps in the intermetallic medium layers. Compared with the prior art, the height of the grooves comprises the height of the conductive layer and a part of the height of the intermetallic medium layers, so that the depth-to-width ratio of the grooves between the adjacent interconnection lines is increased, the air gaps formed in the intermetallic medium layers inside the grooves are larger, stray capacitance is reduced and even removed, and the properties of the semiconductor device can be improved.

A capacitive touch panel that detects an input position accurately with a limited number of sensing electrodes is provided. First and second sensing electrodes adjacent to each other in a detecting direction are arranged such that among a plurality of branch patterns of the first sensing electrode a branch pattern closer to the second sensing electrode, and among a plurality of branch patterns of the second sensing electrode a branch pattern closer to the first sensing electrode are alternately arranged in the detecting direction. The widths in the detecting direction of the plurality of branch patterns of each sensing electrode are set such that the branch patterns on the opposite sides in the detecting direction have the smallest width, and the width of a branch pattern gradually becomes greater as the branch pattern gets closer to a branch pattern at the center.