39results about How to "Suppress signal delay" patented technology

The transistor array substrate of the present invention reduces the voltage drop of wiring. The transistor array substrate includes: a substrate; a plurality of driving transistors arranged in a matrix on the substrate, and a gate insulating film is sandwiched between the gate, the source, and the drain; a plurality of signal lines connected to the The gates of a plurality of drive transistors are laid out together and arranged to extend in a predetermined direction on the substrate; a plurality of supply lines are laid out together with the sources and drains of the drive transistors, and are arranged across the gates. The electrode insulating film is arranged crosswise with the plurality of signal lines, and conducts with one of the source and drain of the driving transistor; a plurality of power supply wirings are respectively stacked on the plurality of supply lines along the plurality of supply lines .

The invention provides a shift register which can operate normally while suppressing a delay of signal and a rounding of waveform. The shift register of the invention includes a plurality of stages of flip-flop circuits each of which includes a clocked inverter. The clocked inverter includes a first transistor and a second transistor which are connected in series, a first compensation circuit including a third transistor and a fourth transistor which are connected in series, and a second compensation circuit including a fifth transistor and a transmission gate. According to the first compensation circuit, a timing at which a signal outputted from the flip-flop circuit rises or falls can be controlled in synchronization with an output of two stages before. The second compensation circuit can control a clock signal input can be controlled.

An electromagnetic transceiver apparatus for a NMR apparatus has an intermediate frequency generator for preparing an intermediate wave, a transmission frequency converter for preparing, on the basis of an intermediate frequency of the intermediate wave, an electromagnetic wave to be radiated from a transmitter coil, a reception frequency converter for processing a signal received by the NMR probe, an analog-digital converter for converting an output of the reception frequency converter into a digital signal, an IQ detector for performing detection on the basis of an output of the analog-digital converter, a phase locked loop and a switch inserted between the analog-digital converter and the reception frequency converter to select either an input from the intermediate frequency generator or an input from the reception frequency converter.

A transmission apparatus, a signal sending apparatus, and a signal receiving apparatus, and a transmission method, a signal sending method, and a signal receiving method capable of solving a problem of metastability and suppressing a delay of a signal when sending and receiving apparatuses having different operation clock frequencies send / receive the signal representative of control information, for example. Included are a sending part that operates in synchronization with a first clock having a first period to output a transmission signal having a signal level that is inverted in response to an input of a first pulse signal corresponding to the first period and a receiving part that operates in synchronization with a second clock having a second period to output a second pulse signal corresponding to the second period in response to inversion of a signal level of the transmission signal.

The present invention provides a printed wiring board, where insulation layers and conductive circuits are laminated alternately, the cross-section of each conductive circuit is rectangular, and when the upper conductive circuit space between adjacent conductive circuits of the PWB is referred to as (W1) and the lower conductive circuit space as (W2), the difference between those spaces with reference to the conductive circuit thickness (T) satisfies the formula 0.10T <=||W1 - W2| |<=0.73T. The above-described structure can suppress crosstalk and delayed signal transmission and prevent malfunctions of ICs even when high-speed driven ICs are mounted.

In a gateway apparatus for interconnecting different types of communication networks that are a line network and a packet network, a method and an apparatus for eliminating sound interruptions that would otherwise occur due to delay or loss of sound encoded data, minimizing the degradation of sound quality, and maintaining a short delay for telephone communication. A sound data processing circuit (550) of the gateway apparatus compares an expected value of the number of sound encoded data as expected outputs to be developed from a multiplexed-data separating circuit (200) in a unit period with the actual number of sound encoded data. If the actual number of sound encoded data is below the expected value, then the sound data processing circuit (550) generates encoded data for causing a destination terminal to execute an error encapsulation, and packetizes and transmits the generated encoded data together with the sound encoded data to the packet network from a transmission circuit (801). If acquiring no sound data from a reception circuit of the packet network in a given period, the sound data processing circuit (550) generates a signal indicative of no acquisition, selects either generation or disposal of the encoded data, and sends the signal to the line network from a data multiplexing circuit (900) and a line network terminating circuit (100).

A high voltage operating field effect transistor is formed in an IC or LSI by utilizing a constituent portion of a transistor or a process technique for a standard power supply voltage of the IC or LSI. In order to increase an operating voltage of a field effect transistor, measures are taken in which a gate is divided into division gates, and electric potentials which are closer to a drain electric potential and which change according to increase or decrease in the drain electric potential are supplied to the division gates nearer a drain, respectively.