The invention discloses a
clock commutation circuit, which resolves technical problem of producing bur and metastable state. The
clock commutation circuit of the invention is composed of two reset producing circuits, two OR gates, three NOT gates, two D-flip-
flops and a
clock output circuit, the reset producing circuits and the NOT gates constitutes a RS latch. Compared with the prior technology, when the first clock is switched to the second clock, the gating
signal of the first clock is switched off when the first clock is at a low level, meanwhile the reset outputting
signal of the second RS latch is released, the gating
signal of the second clock is switched-on when the second clock is at a low level, thereby avoiding the bur during the clock switch. The reset producing circuit ensures that the asynchronous reset terminal of the D-flip-flop executes the synchronization operation to the reset signal through the RS latch circuit when the clock is at a low level, thereby avoiding the production of metastable state.