Three-dimensional vertical NOR Flash Thin-Film Transistor Strings

Abstract

A memory structure, includes active columns of polysilicon formed above a semiconductor substrate, each active column includes one or more vertical NOR strings, with each NOR string having thin-film storage transistors sharing a local source line and a local bit line, the local bit line is connected by one segment of a segmented global bit line to a sense amplifier provided in the semiconductor substrate.

Description

CROSS REFERENCE TO RELATED APPLICATIONS[0001]The present application is a continuation-in-part application of copending U.S. patent application (“Non-Provisional application I”), Ser. No. 16 / 107,732, entitled “Three-dimensional vertical NOR Flash Thin-Film Transistor Strings,” filed on Aug. 21, 2018, which is a continuation application of U.S. patent application Ser. No. 15 / 837,734 entitled “Three-dimensional vertical NOR Flash Thin-Film Transistor Strings,” filed on Dec. 11, 2017, now U.S. Pat. No. 10,096,364, which is a divisional application of U.S. patent application, Ser. No. 15 / 343,332, entitled “Three-dimensional vertical NOR Flash Thin-Film Transistor Strings,” filed on Nov. 4, 2016, now U.S. Pat. No. 9,842,651, which claims priority of (i) U.S. provisional patent application (“Provisional application I”), Ser. No. 62 / 260,137, entitled “Three-dimensional Vertical NOR Flash Thin-film Transistor Strings,” filed on Nov. 25, 2015; (ii) copending U.S. non-provisional patent appli...

AI Technical Summary

Benefits of technology

The present invention relates to a memory structure that includes vertical NOR string arrays with many more TFTs, which allows for faster sensing and minimized program-disturb or read-disturb conditions. The variation in threshold voltages of TFTs within a vertical NOR string can be compensated by providing one or more electrically programmable reference vertical NOR strings in the same or another multi-gate vertical NOR string array. The charge-trapping material of each TFT may have its structure modified to provide a high write / erase cycle endurance, as needed for storing more than one bit in each TFT. The organization of TFTs as vertical NOR strings results in reduced read-latency, sensitivities, and cost per bit as compared to conventional DRAM or NAND string arrays. The vertical NOR strings also provide improved energy utilization and reduced latency in accessing stored data. The patent text also mentions an alternative embodiment that includes multiple, shorter global bit line segments to further reduce read sensitivity and improve the performance of the memory structure.

Problems solved by technology

Thin film NAND transistors have lower conductivity than NAND transistors formed in single crystal silicon, therefore the low read current that is required to be conducted through a long string of NAND TFTs results in a relatively slow read access (i.e. long latency).

Channel hot-electron injection programming requires a relatively large electron current to flow through the channel region, therefore limiting the number of transistors that can be programmed in parallel.

Fowler-Nordheim tunneling and direct tunneling are orders of magnitude more efficient than channel hot-electron injection, allowing massively parallel programming; however, such tunneling is more susceptible to program-disturb conditions.

Furthermore, the polysilicon thin films upon which a vertical NAND string is formed have much lower channel mobility—and therefore higher resistivity—than conventional NAND strings formed in a single-crystal silicon substrate, thereby resulting in a low read current relative to the read current of a conventional NAND string.

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