A
single chip microcomputer comprises a
central processing unit (CPU) 2, a on-
chip RAM 3, a on-
chip ROM 5, a first
bus DBUS for connecting the CPU, RAM, and ROM with one another and transferring data between them, a second
bus ABUS for passing address data corresponding to the data passed through the first
bus, a third bus SDBUS for connecting the CPU 2 with the RAM 3 and transferring data between them, the number of bits of the third bus SDBUS being larger than that of the first bus DBUS, and a fourth bus BABUS for connecting the CPU 2 with the RAM 3 and passing address data corresponding to the data passed through the third bus SDBUS. The CPU 2 has a
data memory RF serving as
general purpose registers for providing internal data to the third bus SDBUS, and a
bank specifying register BP for holding positional data of a mapping region in the RAM 3 where the contents of the
data memory RF are mapped and providing the positional data to the fourth bus BABUS. The RAM 3 has a
memory cell array 31, a
bank address control circuit 35 connected to the fourth bus BABUS, for generating a real address according to the contents of the
bank specifying register BP (BP0, BP1), and a selection circuit 37 for selecting the real address generated by the bank
address control circuit 35, or the address provided through the second bus ABUS.