1095results about How to "Reduce dislocation density" patented technology

A nitride-based semiconductor element having superior mass productivity and excellent element characteristics is obtained. This nitride-based semiconductor element comprises a substrate comprising a surface having projection portions, a mask layer formed to be in contact with only the projection portions of the surface of the substrate, a first nitride-based semiconductor layer formed on recess portions of the substrate and the mask layer and a nitride-based semiconductor element layer, formed on the first nitride-based semiconductor layer, having an element region. Thus, the first nitride-based semiconductor layer having low dislocation density is readily formed on the projection portions of the substrate and the mask layer through the mask layer serving for selective growth. When the nitride-based semiconductor element layer having the element region is grown on the first nitride-based semiconductor layer having low dislocation density, a nitride-based semiconductor element having excellent element characteristics can be readily obtained. The first nitride-based semiconductor layer is formed through only single growth on the substrate, whereby a nitride-based semiconductor element having excellent mass productivity is obtained.

A method of reducing threading dislocation densities in non-polar such as a-{11-20} plane and m-{1-100} plane or semi-polar such as {10-1n} plane III-Nitrides by employing lateral epitaxial overgrowth from sidewalls of etched template material through a patterned mask. The method includes depositing a patterned mask on a template material such as a non-polar or semi polar GaN template, etching the template material down to various depths through openings in the mask, and growing non-polar or semi-polar III-Nitride by coalescing laterally from the tops of the sidewalls before the vertically growing material from the trench bottoms reaches the tops of the sidewalls. The coalesced features grow through the openings of the mask, and grow laterally over the dielectric mask until a fully coalesced continuous film is achieved.

In accordance with the present invention, improved methods for reducing the dislocation density of nitride epitaxial films are provided. Specifically, an in-situ etch treatment is provided to preferentially etch the dislocations of the nitride epitaxial layer to prevent threading of the dislocations through the nitride epitaxial layer. Subsequent to etching of the dislocations, an epitaxial layer overgrowth is performed. In certain embodiments, the etching of the dislocations occurs simultaneously with growth of the epitaxial layer. In other embodiments, a dielectric mask is deposited within the etch pits formed at the dislocations prior to the epitaxial layer overgrowth.

A nitride semiconductor crystal substrate is produced by forming a network mask repeating a closed loop unit shape upon an undersubstrate, growing a nitride semiconductor crystal in vapor phase, producing convex facet hills covered with facets on exposed parts Π, forming outlining concavities on mask-covered parts not burying the facets, maintaining the convex facet hills on Π and the network concavities on excluding dislocations in the facet hills down to the outlining concavities on forming a defect accumulating region H on decreasing dislocations in the facet hills and improving the facet hills to low defect density single crystal regions Z, producing a rugged nitride crystal, and slicing and polishing the nitride crystal into mirror nitride crystal wafers. After the fabrication of devices on the nitride wafer, dry-etching or wet etching of hot KOH or NaOH divides the device-carrying wafer into chips by corroding the network defect accumulating region H.

The invention relates to the semiconductor technical field and discloses a method for manufacturing a nanometer pattern substrate used for the epitaxial growth of a nitride. The method comprises the followings steps: settling a layer of silicon dioxide or silicon nitride film on a substrate used for the epitaxial growth of the nitride; the silicon dioxide or silicon nitride film is coated with a layer of thin metal layer through vapor deposition; conducting the annealing heat treatment, and forming uniformly distributed nano-scaled metal particles; utilizing the formed nano-scaled metal particles as masks to etch the silicon dioxide or silicon nitride film so as to form a nanometer pattern structure; using the silicon dioxide or silicon nitride film with the nanometer pattern structure as a mask etching substrate to transfer the nanometer pattern structure of the substrate; and etching to remove the silicon dioxide or silicon nitride film, cleaning the substrate, and obtaining the nanometer pattern substrate. The invention can reduce the dislocation density in the epitaxial layer of the nitride, improve the crystal quality of epitaxial materials, improve the performance of devices and help to realize the scaled and large area manufacture.

A method of manufacturing a group III nitride semiconductor substrate includes the growth step of epitaxially growing a first group III nitride semiconductor layer on an underlying substrate, and the process step of forming a first group III nitride semiconductor substrate by cutting and / or surface-polishing the first group III nitride semiconductor layer. In the growth step, at least one element selected from the group consisting of C, Mg, Fe, Be, Zn, V, and Sb is added as an impurity element by at least 1×1017 cm−3 to the first group III nitride semiconductor layer. A group III nitride semiconductor substrate having controlled resistivity and low dislocation density and a manufacturing method thereof can thus be provided.

A new and refined method to produce α-Al2O3 layers in a temperature range of from about 750 to about 1000° C. with a controlled growth texture and substantially enhanced wear resistance and toughness than the prior art is disclosed. The α-Al2O3 layer of the present invention is formed on a bonding layer of (Ti,Al)(C,O,N) with increasing aluminium content towards the outer surface. Nucleation of α-Al2O3 is obtained through a nucleation step being composed of short pulses and purges consisting of Ti / Al-containing pulses and oxidising pulses. The α-Al2O3 layer according to the present invention has a thickness ranging from about 1 to about 20 μm and is composed of columnar grains. The length / width ratio of the alumina grains is from about 2 to about 12, preferably from about 4 to about 8. The layer is characterized by a strong (104) growth texture, measured using XRD, and by low intensity of (012), (110), (113), (024) and (116) diffraction peaks.

A refined method to produce textured α-Al2O3 layers in a temperature range of 750-1000° C. with a controlled texture and substantially enhanced wear resistance and toughness than the prior art is disclosed. The α-Al2O3 layer is formed on a bonding layer of (Ti,Al)(C,O,N) with increasing aluminium content towards the outer surface. Nucleation of α-Al2O3 is obtained through a nucleation step composed of short pulses and purges of Ti-containing and oxidizing steps. The α-Al2O3 layer has a thickness ranging from 1 to 20 μm and is composed of columnar grains. The length / width ratio of the alumina grains is from 2 to 15, preferably 6 to 10. The layer is characterised by a strong (110) growth texture, measured using XRD, and by the low intensity of (012), (104), (113), (024) and (116) diffraction peaks.

The invention relates to a preparation method for a graph underlay used for the epitaxial growth of a nitride with high crystal quality, which is characterized by including the steps of: step 1: depositing a layer of thin metal layer on the underlay; step 2: carrying out annealing treatment to lead the thin metal layer to form the amorphous graph of a metal mask with a micron dimension by self organizing; step 3: carrying out dry etching to transfer the graph of the metal mask to the underlay; step 4: removing the residual metal mask by adopting a method for wet corrosion and washing the underlay to prepare and finish the graph underlay.

A semiconductor light-emitting device which includes: a single-crystal substrate formed with a plurality of projection portions on a c-plane main surface; an intermediate layer which is formed to cover the main surface of the single-crystal substrate, in which a film thickness t2 on the projection portion is smaller than a film thickness t1 on the c-plane surface, in which the film thickness t2 on the projection portion is 60% or more of the film thickness t1 on the c-plane surface, and which includes AlN having a single-crystal phase on the c-plane surface and a polycrystalline phase on the projection portion; and a semiconductor layer which is formed on the intermediate layer and includes a group III nitride semiconductor.

The invention presents a tube core shape design with high luminous efficiency, which comprises: epitaxial growing on island area LED chip with discrete grain; after laser peeling, packaging discrete chip into LED with vertical structure and high luminous efficiency. Wherein, the epitaxial growth improves crystal quality and internal quantum efficiency; the shape of island area increases LED light power; the island growth benefits to release stress, reduce stress on interface between GaN and sapphire substrate and the damage and spectral shift during peeling, thereby, it can obtain LED with high performance.