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Semiconductor structure having reduced silicide resistance between closely spaced gates and method of fabrication

A semiconductor structure comprising a plurality of gates located on a semiconductor substrate; wherein insulating spacer is provided on sidewalls of the gates; and metallic silicide located between the gates is provided along with a method for its fabrication. A partially disposable spacer permits increased area for silicide formation without degrading the device short channel behavior.
Owner:IBM CORP

Method for production of a multi-layer analysis element

The invention relates to a method for production of a multi-layer analysis element for liquid samples, with at least one test field for the analysis of the liquid samples, in which method an analysis element blank composed of at least two superposed material layers is made available. The multi-layer analysis element or a constituent part of the multi-layer analysis element is cut out from the analysis element blank by means of laser radiation. The laser radiation cuts through different material layers in at least two areas and has a laser power which is effective for the cutting and which is varied as a function of the thickness and the material of the different material layers to be cut in the areas.
Owner:ROCHE DIABETES CARE INC
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