843results about How to "Increased process window" patented technology

Provided are methods of trimming a photoresist pattern. The methods comprise: (a) providing a semiconductor substrate; (b) forming a photoresist pattern on the substrate, wherein the photoresist pattern is formed from a chemically amplified photoresist composition comprising: a matrix polymer comprising an acid labile group; a photoacid generator; and a solvent; (c) coating a photoresist trimming composition on the substrate over the photoresist pattern, wherein the trimming composition comprises: a matrix polymer, an aromatic acid that is free of fluorine; and a solvent; (d) heating the coated substrate, thereby causing a change in polarity of the photoresist matrix polymer in a surface region of the photoresist pattern; and (e) contacting the photoresist pattern with a rinsing agent to remove the surface region of the photoresist pattern, thereby forming a trimmed photoresist pattern. The methods find particular applicability in the manufacture of semiconductor devices.

In a particular illustrative embodiment, a method of forming a magnetic tunnel junction (MTJ) device is disclosed that includes forming a trench in a substrate. The method further includes depositing a magnetic tunnel junction (MTJ) structure within the trench. The MTJ structure includes a bottom electrode, a fixed layer, a tunnel barrier layer, a free layer, and a top electrode. The method also includes planarizing the MTJ structure. In a particular example, the MTJ structure is planarized using a Chemical Mechanical Planarization (CMP) process.

A manufacturing method of a semiconductor device includes the following steps. First, a substrate is provided. At least one sacrificial gate structure is formed on the substrate, at least one diffusion region is formed in the substrate at each of two sides of the sacrificial gate structure, and a first inter-layer dielectric layer is formed to cover the diffusion region. A gate recess is then formed in the sacrificial gate structure. A first diffusion contact hole is then formed in the first inter-layer dielectric layer and at least partially exposes the diffusion region. A metal layer is subsequently formed in the gate recess and the first diffusion contact hole.

A high efficiency light-emitting diode and a method for manufacturing the same are described. The high efficiency light-emitting diode comprises: a permanent substrate; a first contact metal layer and a second contact metal layer respectively deposed on two opposite surfaces of the permanent substrate; a bonding layer deposed on the second contact metal layer; a diffusion barrier layer deposed on the bonding layer, wherein the permanent substrate, the bonding layer and the diffusion barrier layer are electrically conductive; a reflective metal layer deposed on the diffusion barrier layer; a transparent conductive oxide layer deposed on the reflective metal layer; an illuminant epitaxial structure deposed on the transparent conductive oxide layer, wherein the illuminant epitaxial structure includes a first surface and a second surface opposite to the first surface; and a second conductivity type compound electrode pad deposed on the second surface of the illuminant epitaxial structure.

The present invention provides a number of innovations in the area of computational process control (CPC). CPC offers unique diagnostic capability during chip manufacturing cycle by analyzing temporal drift of a lithography apparatus/ process, and provides a solution towards achieving performance stability of the lithography apparatus/process. Embodiments of the present invention enable optimized process windows and higher yields by keeping performance of a lithography apparatus and/or parameters of a lithography process substantially close to a pre-defined baseline condition. This is done by comparing the measured temporal drift to a baseline performance using a lithography process simulation model. Once in manufacturing, CPC optimizes a scanner for specific patterns or reticles by leveraging wafer metrology techniques and feedback loop, and monitors and controls, among other things, overlay and/or CD uniformity (CDU) performance over time to continuously maintain the system close to the baseline condition.

A technology for manufacturing an interlaced back contact (IBC) crystalline silicon solar battery with ion implantation comprises the following steps: (1) selecting a crystalline silicon base body to perform surface texturing; (2) forming a homotype doping layer having the same electrical property with the base body on the positive surface; (3) forming n+ doping regions and p+ doping regions interlaced to each other on the back surface of the crystalline silicon by the ion implantation; (4) insulating the n+ doping regions and the p+ doping regions on the back surface of the crystalline silicon base body; (5) performing annealing in order to eliminate crystalline damage caused by iron implantation to the crystalline silicon base body, and performing thermal oxidation to form a SiOx oxide layer; (6) forming a passive anti-reflecting film on the positive surface of a silicon chip; (7) forming a passive film on the back surface of the silicon chip; and (8) forming an emitter and a metal contact electrode of a base electrode on the back surface, and forming the ohmic contact of the metal electrode with the n+ doping regions and the p+ doping regions after one sintering. The method canaccurately control concentration, depth and position of the doping, and the technological process is simple, and easy to operate.

A method of fabricating polycrystalline silicon layer of TFT is provided. The method includes sequentially forming an insulating layer, a first amorphous silicon layer, and a cap layer on a substrate. A laser annealing is performed to transform the first amorphous silicon layer to a first polycrystalline silicon layer, wherein at least one hole is formed in the amorphous silicon layer during the laser annealing process. Thereafter, the cap layer is removed. A portion of the insulating layer exposed within the hole is removed to form a second opening. A second amorphous silicon layer is formed over the first polycrystalline silicon layer filling the second opening. Finally a second annealing is performed to transform the second amorphous silicon layer to a second polycrystalline silicon layer.

The invention discloses a preparation method of a double-sided passivated crystalline silicon solar cell, belonging to the technical field of photovoltaic power generation. The preparation method comprises the following steps of: firstly, respectively carrying out surface precleaning and surface texturing on P-shaped single crystal silicon and a polycrystalline silicon wafer by adopting an alkaline solution and an acid solution; secondly, diffusing by using phosphorus oxychloride as a diffusion source to form a PN junction; thirdly, removing a phosphosilicate glass on the surface of the silicon wafer by adopting a chemical wet method, and etching the edge of the silicon wafer by adopting a plasma; fourthly, preparing a silicon nitride film on the surface of an emitting region of a P-type silicon wafer by adopting a plasma enhanced chemical vapor deposition method; fifthly, preparing a mixed phase film material of hydrogenated microcrystalline silicon and amorphous silicon by adopting a hot filament chemical vapor deposition method, depositing a film at one side of the P-type silicon wafer, and passivating the defects and a dangling bond on the surface of the P-type silicon wafer; and sixthly, sintering a screen printing back electrode and a screen printing positive electrode to form the solar cell. The invention lowers the probability of compounding photo-generated minority carriers on the back surface, enhances the long-wave light quantum efficiency and creates the conditions of transportation and collection of the photo-generated carriers.

Embodiments of a computer system, a process, a computer-program product (i.e., software), and a data structure or a file for use with the computer system are described. These embodiments may be used to determine or generate source patterns that define illumination patterns on photo-masks during a photolithographic process. Moreover, a given source pattern may be determined concurrently with an associated mask pattern (to which a given photo-mask corresponds) or sequentially (i.e., either the given source pattern may be determined before the associated mask pattern or vice versa.). During the determining, the given source pattern may be represented using one or more level-set functions. Additionally, the source pattern may be determined using an Inverse Lithography (ILT) calculation.

A method of designing a mask for imaging an integrated circuit (IC) design layout is provided to efficiently configure subresolution assist features (SRAFs) corresponding to an optimally configured annular illumination source of a lithographic projection system. A critical pitch is identified for the IC design, and optimal inner and outer radial coordinates of an annular illumination source are determined so that the resulting image projected through the mask will be optimized for the full range of pitches in the design layout. A relationship is provided for determining an optimal inner radius and outer radius for the annular illumination source. The number and placement of SRAFs are added to the mask design so that the resulting range of pitches substantially correspond to the critical pitch. The method of configuring SRAFs so that the image will have optimal characteristics, such as good contrast and good depth of focus, is fast.

Reactive ion etch (RIE) selectivity during etching of a feature nearby embedded structure is improved by using a silicon oxynitride layer formed with carbonization throughout layer.