276results about How to "Good etching" patented technology

The present invention discloses a process for depositing a carbon containing silicon oxide film, or a carbon containing silicon nitride film having enhanced etch resistance. The process comprises using a silicon containing precursor, a carbon containing precursor and a chemical modifier. The present invention also discloses a process for depositing a silicon oxide film, or silicon nitride film having enhanced etch resistance comprising using an organosilane precursor and a chemical modifier.

A method of depositing an oxide film on a template for patterning in semiconductor fabrication, includes: (i) providing a template having patterned structures thereon in a reaction space; and (ii) depositing an oxide film on the template by plasma-enhanced atomic layer deposition (PEALD) using nitrogen gas as a carrier gas and also as a dilution gas, thereby entirely covering with the oxide film an exposed top surface of the template and the patterned structures.

The present invention is directed to a method of forming an FeRAM integrated circuit, which includes performing a capacitor stack etch to define the FeRAM capacitor. The method comprises etching a PZT ferroelectric layer with a high temperature BCl₃ etch which provides substantial selectivity with respect to the hard mask. Alternatively, the PZT ferroelectric layer is etch using a low temperature fluorine component etch chemistry such as CHF₃ to provide a non-vertical PZT sidewall profile. Such a profile prevents conductive material associated with a subsequent bottom electrode layer etch from depositing on the PZT sidewall, thereby preventing leakage or a “shorting out” of the resulting FeRAM capacitor.

In a particular illustrative embodiment, a method of forming a magnetic tunnel junction (MTJ) device is disclosed that includes forming a trench in a substrate. The method further includes depositing a magnetic tunnel junction (MTJ) structure within the trench. The MTJ structure includes a bottom electrode, a fixed layer, a tunnel barrier layer, a free layer, and a top electrode. The method also includes planarizing the MTJ structure. In a particular example, the MTJ structure is planarized using a Chemical Mechanical Planarization (CMP) process.

The invention relates to a mask plate and a manufacture method thereof. The mask plate comprises a lightproof region, a fully transparent region and a partial transparent region; the partial transparent region is formed in a such way that a semi-transparent part and a transparent part are alternatively arranged. The invention is a new mask plate manufactured by combining a grey mask plate technique and halftone mask plate technique; the mask plate ensures that the exposure of photoresist at the lower part of the partial nonopaque region is uniform when in use, which is beneficial to forming the smooth surface of a partial maintaining region of the photoresist, thereby facilitating the TFT groove etch and improving the yield of array substrates, at the same time, the obliquity of the photoresist at the edge of the partial maintaining region of the photoresist is increased, thereby the technique can be accurately controlled in the process of forming the TFT groove.

A semiconductor device is provided, including two semiconductor nanowires superimposed one on top of the other or arranged next to one another, spaced one from the other and forming channel regions of the semiconductor device, a dielectric structure entirely filling a space between the nanowires and which is in contact with the nanowires, a gate dielectric and a gate covering a first of the nanowires, sidewalls of the nanowires and sidewalls of the dielectric structure when the nanowires are superimposed one on top of the other, or covering a part of the upper faces of the nanowires and a part of an upper face of the dielectric structure when the nanowires are arranged next to one another, and wherein the dielectric structure comprises a portion of dielectric material with a relative permittivity greater than or equal to 20.

A method and apparatus for detecting the endpoint in a dry plasma etching system comprising a first electrode (e.g., upper electrode) and a second electrode (e.g., lower electrode) upon which a substrate rests is described. A direct current (DC) voltage is applied between the first electrode and a ring electrode surrounding the second electrode, and the DC current is monitored to determine the endpoint of the etching process. The DC current is affected by the impedance of the plasma, and therefore responds to many variations including, for example, the plasma density, electron/ion flux to exposed surfaces, the electron temperature, etc.

Provided is a copper foil for a printed wiring board including a roughened layer on at least one surface thereof. In the roughened layer, the average diameter D1 at the particle bottom being apart from the bottom of each particle by 10% of the particle length is 0.2 to 1.0 μm, and the ratio L1/D1 of the particle length L1 to the average diameter D1 at the particle bottom is 15 or less. In the copper foil for printed wiring board, when a copper foil for printed wiring having a roughened layer is laminated to a resin and then the copper layer is removed by etching, the sum of areas of holes accounting for the resin roughened surface having unevenness is 20% or more. The present invention involves the development of a copper foil for a semiconductor package substrate that can avoid circuit erosion without causing deterioration in other properties of the copper foil. In particular, an object of the present invention is to provide a copper foil for a printed wiring board and a method of producing the copper foil, in which the adhesion strength between the copper foil and the resin can be enhanced by improvement of the roughened layer of the copper foil.

The invention relates to a frosting liquid, a preparation method and uses thereof, and an anti-glare glass preparation method, and provides a frosting liquid, which is prepared by mixing the followingraw materials by weight: 10-17 parts of ammonium fluoride, 7-12 parts of sulfuric acid, 3-5 parts of calcium fluoride, 3-5 parts of ammonium sulfate, 15-20 parts of potassium sulfate, and 130-140 parts of water. The invention further provides the an anti-glare glass preparation method, which comprises: (1) placing a glass in a frosting liquid; and (2) introducing a gas into the frosting liquid, and carry out a reaction. According to the present invention, the anti-glare glass prepared by using the frosting liquid through the preparation method has advantages of high light transmittance, highgloss, fine surface particles, uniform particle distribution and the like.

Disclosed is a method for fabricating a transistor of a memory device capable of preventing voids from being created when forming a low-resistant gate electrode. The method includes the steps of forming an active area by etching a semiconductor substrate, forming a field oxide layer in the semiconductor substrate and forming a recess by etching the field oxide layer. A gate insulation layer is formed along an upper surface of the active area and an exposed portion of the active area. A gate electrode is formed on the field oxide layer such that the gate electrode extends across an upper portion of the active area while being overlapped with a channel area and the recess. The first conductive layer to be patterned has the same thickness, so the low-resistant gate electrode is easily fabricated without forming the voids.

A shadow mask blank of Fe-Ni alloy which exhibits excellent uniformity of diameter of apertures formed by perforation with etching for the passage of electron beams, consisting of 34-38% Ni, 0.05-0.5% Mn, 4-20 ppm S, and the balance Fe and no more than specified limits of C, Si, Al, and P, with MnS inclusions 50-1,000 nm in diameter dispersed at the density of at least 1,500/mm2 or simply with etched holes 0.5-10 mum in diameter emerging at the density of at least 2,000/mm2 when the blank is immersed in a 3% nitric acid-ethyl alcohol solution at 20° C. for 30 seconds. A method of manufacturing the blank comprises hot rolling of a slab of the Fe-Ni alloy, cooling, recrystallization annealing, cold rolling, etc. under controlled conditions: e.g., hot rolling the slab at 950-1,250° C. to 2-6 mm thick, cooling the stock in the range of 900-700° C. at the rate of 0.5° C./second, continuously passing the stock through a heating furnace at 850-1,100° C. for recrystallization annealing to adjust the mean diameter of the recrystallized grains to 5-30 mum, and performing the cold rolling before the final recrystallization annealing at a reduction ratio of 50-85% and the final cold rolling at a reduction ratio of 10-40%.

The present invention provides an etchant, capable of preventing dimensional precision of a wiring pattern from reducing when removing a chemical copper plate in a half addition process. A first etchant of the invention is characterized in that it is a copper etchant containing sulphuric acid, hydogen peroxide and water, and containing more than two benzotriazole derivates containing at least oneof carboxyl and dydroxyl in a molecule. A second etchant of the invention is characterized in that it is a copper etchant containing sulphuric acid, hydogen peroxide and water, and containing pyrrolehaving heteroatom of nitrogen atom only in a loop, and polyprotic acid having more than two carboxyl or salts thereof.