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Pedestrian inertial positioning system based on indoor magnetic field feature assistance

The invention provides a pedestrian inertial positioning system based on indoor magnetic field feature assistance. The system comprises a magnetic field and inertial data obtaining module, a magnetic field positioning module, a pedestrian dead reckoning module, a positioning fusion module and an output module, wherein the magnetic field and inertial data obtaining module is used for acquiring magnetic field, accelerated speed and angular velocity information; the magnetic field positioning module is used for building a magnetic field feature library and carrying out time-frequency analysis on the magnetic field vector sequence in real time to extract the time-frequency feature, and matching with the magnetic field feature library to carry out magnetic field feature positioning; the pedestrian dead reckoning module is used for updating accelerated speed and angular velocity zero offset according to the condition that the step velocity discontinuity is zero during walking, judging the step number and calculating the step length and the direction of each step; the positioning fusion module is used for fusing a magnetic field feature positioning result and a pedestrian dead reckoning inertial positioning result by means of particle filter; and the output module is used for displaying a positioning result on web pages and terminals. The system provided by the invention has the characteristics of being independent from beacon during positioning, low in cost and consumption of positioning terminals, accurate in positioning result and adaptive to environment change.
Owner:MEDIASOC TECH

Stacked type semiconductor memory device and chip selection circuit

A stacked type semiconductor memory device of having a structure in which a plurality of semiconductor chips is stacked and a desired semiconductor chip can be selected by assigning a plurality of chip identification numbers different from each other are individually assigned to the plurality of semiconductor chips comprising: a plurality of operation circuits which is connected in cascade in a stacking order of the plurality of semiconductor chips and outputs the plurality of identification numbers different from each other by performing a predetermined operation; and a plurality of comparison circuits which detects whether or not each the identification number and a chip selection address commonly connected to each the semiconductor chip are equal to each other by comparing them.
Owner:PS4 LUXCO SARL

Cross-layer design techniques for interference-aware routing configuration in wireless mesh networks

Methods, apparatuses and systems directed to facilitating increased throughput in wireless mesh networks. Generally, according to one implementation of the present invention, routing nodes in a wireless mesh network combine metrics corresponding to the link and network layers to select a route to a root node in the wireless mesh network. In one implementation, for each neighbor, a given routing node computes a routing metric, which is based on the computed route cost and hop count, and selects a preferred neighbor as the parent routing node based on the best routing metric.
Owner:CISCO TECH INC
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