606 results about "Stress induced" patented technology

An optoelectronic device with a Group III Nitride active layer is disclosed that comprises a silicon carbide substrate; an optoelectronic diode with a Group III nitride active layer; a buffer structure selected from the group consisting of gallium nitride and indium gallium nitride between the silicon carbide substrate and the optoelectronic diode; and a stress-absorbing structure comprising a plurality of predetermined stress-relieving areas within the crystal structure of the buffer structure, so that stress-induced cracking that occurs in the buffer structure occurs at predetermined areas rather than elsewhere in the buffer structure.

An optoelectronic device with a Group III Nitride active layer is disclosed that comprises a silicon carbide substrate; an optoelectronic diode with a Group III nitride active layer; a buffer structure selected from the group consisting of gallium nitride and indium gallium nitride between the silicon carbide substrate and the optoelectronic diode; and a stress-absorbing structure comprising a plurality of predetermined stress-relieving areas within the crystal structure of the buffer structure, so that stress-induced cracking that occurs in the buffer structure occurs at predetermined areas rather than elsewhere in the buffer structure.

A substrate under tension and / or compression improves performance of devices fabricated therein. Tension and / or compression can be imposed on a substrate through selection of appropriate gate sidewall spacer material disposed above a device channel region wherein the spacers are formed adjacent both the gate and the substrate and impose forces on adjacent substrate areas. Another embodiment comprises compressive stresses imposed in the plane of the channel using SOI sidewall spacers made of polysilicon that is expanded by oxidation. The substrate areas under compression or tension exhibit charge mobility characteristics different from those of a non-stressed substrate. By controllably varying these stresses within NFET and PFET devices formed on a substrate, improvements in IC performance have been demonstrated.

A semiconductor device has an n channel conductivity type field effect transistor having a channel formation region formed in a first region on one main surface of a semiconductor substrate and a p channel conductivity type field effect transistor having a channel formation region formed in a second region on the main surface of the semiconductor substrate, which second region is different from the first region. An internal stress generated in the channel formation region of the n channel conductivity type field effect transistor is different from an internal stress generated in the channel formation region of the p channel conductivity type field effect transistor. The internal stress generated in the channel formation region of the n channel conductivity type field effect transistor is a tensile stress, while the internal stress generated in the channel formation region of the p channel conductivity type field effect transistor is a compressive stress.

The present invention relates generally to methods for designing and optimizing the number, placement, and size of fractures in a subterranean formation and more particularly to methods that account for stress interference from other fractures when designing and optimizing the number, placement, and size of fractures in the subterranean formation. The present invention optimizes the number, placement and size of fractures in a subterranean formation. The present invention determines one or more geomechanical stresses induced by each fracture based on the dimensions and location of each fracture, including surface deformations caused by each fracture. The present invention determines a maximum number of fractures and a predicted stress field based on the geomechanical stresses induced by each of the fractures.

By recessing a semiconductor layer, preferably by locally oxidizing the semiconductor layer, a stress-inducing material and / or a dopant species may be introduced into the thinned semiconductor layer in the vicinity of a gate electrode structure by means of a subsequent epitaxial growth process. In particular, the stress-inducing material formed adjacent to the gate electrode structure exerts compressive or tensile stress, depending on the type of material deposited, thereby also enhancing the mobility of the charge carriers in a channel region of the transistor element.

Disclosed is a method of proof testing a sheet of brittle material such as a glass or glass-ceramic based material. The method comprises bending the glass sheet over at least one arcuate member to detect sheets having a strength greater than a predetermined value. The method includes imparting a bend to the sheet and producing relative motion between the sheet and the bend such that the bend traverses the sheet, and wherein tensile stress induced in a surface of the sheet by the bend corresponds to the predetermined strength value. An apparatus for performing the proof testing is also disclosed.

A method and device for converting light from a first wavelength to a second wavelength. The method comprises the steps of exciting an electron in a quantum dot with an incident infrared photon having the first wavelength, the excited electron having a first energy, tunneling the excited electron through a barrier into a stress induced quantum dot, and recombining the excited electron with a hole in the stress induced quantum dot, therein producing a photon having the second wavelength, typically in the visible range. The device comprises a substrate, a spacer layer, coupled to the substrate, a second layer, coupled to the spacer layer, wherein the second layer comprises a different material than the spacer layer, a third layer, coupled to the second layer, wherein the third layer comprises at least one quantum dot, a fourth layer, coupled to the third layer, comprising a quantum well corresponding to each quantum dot in the third layer, a fifth layer, coupled to the fourth layer, wherein the fourth layer and fifth layer comprise a strain induced quantum dot corresponding to each quantum dot in the third layer; and a sixth layer, coupled to the fifth layer, the substrate and the sixth layer for contacting the device.

The present invention provides a semiconducting device including at least one gate region including a gate conductor located on a surface of a substrate, the substrate having an exposed surface adjacent the gate region; a silicide contact located adjacent the exposed surface; and a stress inducing liner located on the silicide contact, the exposed surface of the substrate adjacent to the gate region and the at least one gate region, wherein the stress inducing liner provides a stress to a device channel portion of the substrate underlying the gate region. The stress produced on the device channel is a longitudinal stress on the order of about 200 MPa to about 2000 MPa. The present invention also provides a method for forming the above-described semiconducting device.

A method (100) of forming a transistor includes forming a gate structure (108) over a semiconductor body and forming recesses (112) using an isotropic etch using the gate structure as an etch mask. The isotropic etch forms a recess in the semiconductor body that extends laterally in the semiconductor body toward a channel portion of the semiconductor body underlying the gate structure. The method further includes epitaxially growing silicon (114) comprising stress-inducing species in the recesses. The source and drain regions are then implanted (120) in the semiconductor body on opposing sides of the gate structure.

A method for manufacturing a thin film direct bandgap semiconductor active solar cell device comprises providing a source substrate having a surface and disposing on the surface a stress layer having a stress layer surface area in contact with and bonded to the surface of the source substrate. Operatively associating a handle foil with the stress layer and applying force to the handle foil separates the stress layer from the source substrate, and leaves a portion of the source substrate on the stress layer surface substantially corresponding to the area in contact with the surface of the source substrate. The portion is less thick than the source layer. The stress layer thickness is below that which results in spontaneous spalling of the source substrate. The source substrate may comprise an inorganic single crystal or polycrystalline material such as Si, Ge, GaAs, SiC, sapphire, or GaN. In one embodiment the stress layer comprises a flexible material.

In a micro-electromechanical structure, a rotor has a centroidal axis and includes a suspended structure which carries mobile electrodes. A stator carries fixed electrodes facing the mobile electrodes. The suspended structure is connected to a rotor-anchoring region via elastic elements. The stator includes at least one stator element, which carries a plurality of fixed electrodes and is fixed to a stator-anchoring region. One of the rotor-anchoring regions and stator-anchoring regions extends along the centroidal axis and at least another of the rotor-anchoring regions and stator-anchoring regions extends in the proximity of the centroidal axis.