2095results about How to "Improve driving ability" patented technology

A high-speed shift register circuit is provided. The shift register circuit includes a first transistor supplying a clock signal to a first output terminal, a second transistor discharging the first output terminal, a third transistor supplying the above clock signal to a second output terminal, and a fourth transistor discharging the second output terminal. The gates of the first and third transistors are both connected to a first node, and the gates of the second and fourth transistors are both connected to a second node. The first node is charged by a fifth transistor which is connected between the first node and a first input terminal and which has a gate connected to a second input end.

Malfunction caused by leakage current of the transistor and shift in threshold voltage is prevented in the shift register in which the signal can be shifted bi-directionally. The bi-directional unit shift register includes a first transistor Q 1 for providing a first clock signal CLK to an output terminal OUT, a second transistor Q 2 for discharging the output terminal OUT based on a second clock signal, third and fourth transistors Q 3 , Q 4 for providing first and second voltage signals Vn, Vr complementary to each other to a first node, which is a gate node of the first transistor Q 1 , and a fifth transistor Q 5 connected between the first node and the output terminal OUT. The fifth transistor Q 5 is in an electrically conducted state based on the first clock signal CLK when the gate of the transistor Q 1 is at L (Low) level.

A field effect transistor can include a vertical channel protruding from a substrate including a source / drain region junction between the vertical channel and the substrate, and an insulating layer extending on a side wall of the vertical channel toward the substrate to beyond the source / drain region junction. The transistor can also include a nitride layer extending on the side wall away from the substrate to beyond the insulating layer, a second insulating layer extending on the side wall that is separated from the channel by the nitride layer, and a gate electrode extending on the side wall toward the substrate to beyond the source / drain region junction. Related methods are also disclosed.

The invention discloses a gate driver on array (GOA) circuit for a liquid crystal display device. The liquid crystal display device comprises multiple scanning lines, and the GOA circuit comprises multiple cascaded GOA units. The Nth scanning line of the display area is charged by a Nth level GOA unit control, and the Nth level GOA unit comprises a forward and reverse scanning control circuit, a pull-up circuit, a bootstrap capacitor circuit, a pull-up control circuit and a drop-down holding circuit. The pull-up circuit, the bootstrap capacitor circuit, the pull-up control circuit and the drop-down holding circuit are connected with a grid signal point. The pull-up circuit, the bootstrap capacitor circuit and the drop-down holding circuit are connected with the Nth scanning line. The forward and reverse scanning control circuit is connected with a (N-1)th scanning line and the (N+1)th scanning line. The GOA circuit for the liquid crystal display device is used for improving the stability of the grid signal point and reducing the usage of transistors.

It is an object of the present invention to control the plane orientation of crystal grains obtained by using a laser beam, into a direction that can be substantially regarded as one direction in an irradiation region of the laser beam. After forming a cap film over a semiconductor film, the semiconductor film is crystallized by using a CW laser or a pulse laser having a repetition rate of greater than or equal to 10 MHz. The obtained semiconductor film has a plurality of crystal grains having a width of greater than or equal to 0.01 μm and a length of greater than or equal to 1 μm. In a surface of the obtained semiconductor film, a ratio of an orientation {211} is greater than or equal to 0.4 within the range of an angle fluctuation of ±10°.

The embodiment of the invention provides a foldable display panel and a display device. The foldable display panel comprises a first non-folding region, a folding region, a second non-folding region,a plurality of grid electrode lines, a plurality of data lines, a plurality of first data lead pins, a plurality of second data lead pins, a plurality of first data lead lines and a plurality of second data lead lines, wherein the first non-folding region, the folding region and the second non-folding region are arranged in the first direction; the first data lead pins are positioned in the firstnon-folding region; the second data lead pins are positioned in the second non-folding region; the grid electrode lines extend from the first non-folding region in the first direction, pass through the folding region and extend to the second non-folding region; the data lines also comprise first data lines and second data lines; the first data lines are electrically connected with the first data lead pins; the second data lines are electrically connected with the second data lead pins. The folding shaft of the foldable display panel is basically parallel to the data lines. The embodiment alsoprovides the foldable display panel and the display device; the arrangement positions of the data lines and the grid electrode lines are exchanged, so that the data lines cannot generate transverse bending; the data lead pins are only positioned in the non-bending region; the panel reliability is improved.