70 results about "Mixed pattern" patented technology

Different sized features in the array and in the periphery of an integrated circuit are patterned on a substrate in a single step. In particular, a mixed pattern, combining two separately formed patterns, is formed on a single mask layer and then transferred to the underlying substrate. The first of the separately formed patterns is formed by pitch multiplication and the second of the separately formed patterns is formed by conventional photolithography. The first of the separately formed patterns includes lines that are below the resolution of the photolithographic process used to form the second of the separately formed patterns. These lines are made by forming a pattern on photoresist and then etching that pattern into an amorphous carbon layer. Sidewall pacers having widths less than the widths of the un-etched parts of the amorphous carbon are formed on the sidewalls of the amorphous carbon. The amorphous carbon is then removed, leaving behind the sidewall spacers as a mask pattern. Thus, the spacers form a mask having feature sizes less than the resolution of the photolithography process used to form the pattern on the photoresist. A protective material is deposited around the spacers. The spacers are further protected using a hard mask and then photoresist is formed and patterned over the hard mask. The photoresist pattern is transferred through the hard mask to the protective material. The pattern made out by the spacers and the temporary material is then transferred to an underlying amorphous carbon hard mask layer. The pattern, having features of difference sizes, is then transferred to the underlying substrate.

An optical device for sensing an incident optical wave within a wavelength range includes a first array and a second array of electrodes superposed on a substrate, and a sensor connected to the contacts. The arrays are interdigitated. Each array includes its own parameters: contact width, contact thickness, groove width, and a groove dielectric constant. A structure associated with the arrays resonantly couples the incident wave and a local electromagnetic resonance or hybrid mode including at least a surface plasmon cavity mode (CM). For coupling the CM, an aspect ratio of contact thickness to spacing between electrodes is at least 1. A preferred structure for coupling a hybrid mode for high bandwidth and responsivity includes a higher dielectric constant in alternating grooves. The substrate may include silicon, including silicon-on-insulator (SOI). An SOI device having a alternating grooves with a higher dielectric, e.g., silicon oxide, provides 0.25 A / W and 30 GHz bandwidth.

A method of implementing a hybrid mode of a multi-core processor includes setting a hybrid mode as a power management mode of the multi-core processor. The hybrid mode includes operating more than one core of the processor and alternately operating only a single core of the processor. The hybrid mode includes operating a first core of the processor and alternately operating a second core of the processor. The hybrid mode of a method, apparatus or computer readable medium includes alternate operation between two or more processor cores of a multi-core processor according to a preset or adjustable operating ratio.