76results about How to "Small line width" patented technology

A transparent holographic display screen for laser projection of at least one or more monochromatic wavelengths, is constructed to selectively diffuse an incident narrow-band laser beam at a predetermined solid angle and simultaneously to pass wide-band ambient light unobstructed through the display screen. The transparent holographic display screen has at least one holographic volume phase grating which is optically coupled to or integrated with a transparent carrier plate. The holographic display screen with its volume grating is produced by illuminating a real screen as an object into a primary hologram and recording a real holographic image of said real screen into a secondary hologram.

The present invention relates to a method for calibrating a metrology stage in at least two dimensions using an artefact plate having marks forming a pattern, comprising the steps of: placing the artefact plate on the metrology stage in at least three positions, assuming the geometrical properties of the metrology stage and the artefact plate, and the positions of the artefact plate for each measurement, forming a model predicting the measurements of the artefact plate, measuring the marks by the metrology stage, and inverting said model to improve the assumptions on metrology stage and artefact plate.

A apparatus and method for creating a universally usable and configurable sensor platform which is used in conjunction with various sensor and sensing elements to sense and measure environmental conditions which incorporates inputs from multiple sensors 6-9 and 12-14. The apparatus incorporates an oscillator 3 which provides a signal whose frequency varies according to the inputs from sensors 6-9 and 12-14 in combination with a microprocessor 1. A cordic block 61 allows for supplemental calculations of trigonometric operations and functions. An output unit 2 converts the signals received from microprocessor 1 into a variety of serial protocols.

The invention discloses a short wave optical thermal detector and a focal plane array device thereof. The short wave optical thermal detector includes an electrode, an electric contact, a photo-thermal detection structure and a substrate. Two ends of the electrode are connected with the electric contact and the photo-thermal detection structure respectively. The photo-thermal detection structure includes heat reactive lines and conducting Na particles capable of generating local surface Plasmon resonance. When electromagnetic radiation of a specific wavelength acts on the conducting Na particles, local surface Plasmon resonance is generated, os that hot spots are formed. Therefore, temperature rise of the heat reactive lines is caused and electric parameter change is caused, and detection of specific electromagnetic radiation by the detector is realized. Through adjusting geometric parameters of the conducting Na particles and combining the conducting Na particles of different parameters, selective spectrum radiation detection and multi-waveband radiation detection are realized. The optical thermal detector provided by the invention is simple in structure and the low cost short wave optical (ultraviolet, visible light and near infrared) waveband detector and the focal plane array device thereof are realized.

When an oxide semiconductor film is microfabricated, with the use of a hard mask, unevenness of a side surface of the oxide semiconductor film can be suppressed. Specifically, a semiconductor device comprises an oxide semiconductor film over an insulating surface; a first hard mask and a second hard mask over the oxide semiconductor film; a source electrode over the oxide semiconductor film and the first hard mask; a drain electrode over the oxide semiconductor film and the second hard mask; a gate insulating film over the source electrode and the drain electrode; and a gate electrode overlapping with the gate insulating film and the oxide semiconductor film, and the first and second hard masks have conductivity.

A apparatus and method for creating a universally usable and configurable sensor platform which is used in conjunction with various sensor and sensing elements to sense and measure environmental conditions which incorporates inputs from multiple sensors 6-9 and 12-14. The apparatus incorporates an oscillator 3 which provides a signal whose frequency varies according to the inputs from sensors 6-9 and 12-14 in combination with a microprocessor 1. A cordic block 61 allows for supplemental calculations of trigonometric operations and functions. An output unit 2 converts the signals received from microprocessor 1 into a variety of serial protocols.

An apparatus (1) serves for linear illumination of a moving product web (6), the apparatus (1) having at least one light source (4) emitting light. In order to achieve high luminance in a linear subregion of the product web (6), at least a portion of the light emitted by the light source (4) is reflected towards the product web (6) by at least one tubular reflector (5). The tubular reflector (5) in this case has at least one light exit slit (7) which is assigned to the product web (6). Moreover, the tubular reflector has at least one observation slit (8) which lies opposite the light exit slit (7). The illuminated product web (6) can be observed through this observation slit (8) by means of a line camera (2).

A method of forming a pattern in a semiconductor device is described. A substrate divided into cell and peripheral regions is provided, and an object layer is formed on a substrate. A buffer pattern is formed on the object layer in the cell region along a first direction. A spacer is formed along a sidewall of the buffer pattern in the cell region, and a hard mask layer remains on the object layer in the peripheral region. The buffer layer is removed, and the spacer is separated along a second direction different from the first direction, thereby forming a cell hard mask pattern. A peripheral hard mask pattern is formed in the peripheral region. A minute pattern is formed using the cell and peripheral hard mask patterns in the substrate. Therefore, a line width variation or an edge line roughness due to the photolithography process is minimized.

The present invention pertains to a method of fabricating a trench capacitor having increased capacitance. To tackle a difficult problem of etching deeper trenches having very high aspect ratio, an epitaxial silicon growth process is employed in the fabrication of next-generation trench DRAM devices. A large-capacitance trench capacitor is first fabricated in the silicon substrate. An epitaxial silicon layer is then grown on the silicon substrate. Active areas, shallow trench isolation regions, and gate conductors are formed on / in the epitaxial silicon layer.

Disclosed are atomic layer deposition method and a semiconductor device including the atomic layer, including the steps: placing a semiconductor substrate in an atomic layer deposition chamber; feeding a first precursor gas to the semiconductor substrate within the chamber to form a first discrete monolayer on the semiconductor substrate; feeding an inert purge gas to the semiconductor substrate within the chamber to remove the first precursor gas which has not formed the first discrete monolayer on the semiconductor substrate; feeding a second precursor gas to the chamber to react with the first precursor gas which has formed the first discrete monolayer, forming a discrete atomic size islands; and feeding an inert purge gas to the semiconductor substrate within the chamber to remove the second precursor gas which has not reacted with the first precursor gas and byproducts produced by the reaction between the first and the second precursor gases.

There is disclosed a chemically-amplified positive resist composition comprising, as main components, (A) a base polymer, which contains one or more kinds of a monomer unit represented by the following general formula (1) and the like, and is an alkali-insoluble polymer whose hydroxyl group is partly protected by an acetal group while alkali-soluble when deprotected by an acid catalyst, (B) a sulfonium salt containing a sulfonate anion, (C) a basic component, and (D) an organic solvent. In a lithography technology by a photo resist, an extremely high temporal stability is necessary. In addition, it must give a good pattern profile not dependent on a substrate and have a high resolution power. There can be provided a chemically-amplified positive resist composition which can solve these problems simultaneously, a resist patterning process using the same, and a method for producing a photo mask blank.

Provided is a process for producing a glass plate with a conductive printed wire, which does not require a screen plate for each model, facilitates adjustments for desired heat generation performance or antenna performance, has an excellent adhesion to a glass plate surface, and minimizes surface roughness.The process for producing a glass plate with a conductive printed wire is characterized in that a laminate comprising a layer obtained by electro printing a first conductive toner having a number standard average particle size (D50) of 10 μm<D50≦50 μm and a layer obtained by electro printing a second conductive toner having a particle size (D50) of 5 μm≦D50≦10 μm is formed on a surface of a glass plate and the glass plate is heated to fire the toners to thereby form a conductive printed wire having a predetermined pattern on the surface of the glass plate.

An array substrate, a display panel, and a display device are provided. The array substrate includes a display region and a non-display region surrounding the display region. The array substrate also includes a plurality of gate lines. The plurality of gate lines include a plurality of regular gate lines and at least one irregular gate line. The plurality of regular gate lines are disposed in the display region and extended along a first direction. The at least one irregular gate line includes at least one first trace portion and a second trace portion electrically connected to each other. The at least one first trace portion has a same line width as a regular gate line of the plurality of regular gate lines, and the second trace portion has a line width smaller than the at least one first trace portion.