3816results about "Galvano-magnetic device manufacture/treatment" patented technology

A method for providing a magnetic element is disclosed. The method includes providing at least one magnetic element layer and providing a hard mask structure for masking a portion of the at least one magnetic element layer. The hard mask structure is made from hard mask material(s) that are etchable for defining the hard mask structure. The hard mask structure also acts as a mask during definition of a width of the magnetic element. The method also includes defining the width of the magnetic element by removing a portion of the at least one magnetic element layer using the hard mask structure as a mask. The hard mask structure preferably acts as a polishing stop for a planarization step, such as a chemical mechanical polish, polishing resistant structures might be provided to improve planarization of a magnetic memory incorporating the magnetic element.

A method of manufacturing a magnetoresistive-based device having magnetic material layers formed between a first electrically conductive layer and a second electrically conductive layer, the magnetic materials layers including a tunnel barrier layer formed between a first magnetic materials layer and a second magnetic materials layer, including removing the first electrically conductive layer and the first magnetic materials layer unprotected by a first hard mask, to form a first electrode and a first magnetic materials, respectively; and removing the tunnel barrier layer, second magnetic materials layer, and second electrically conductive layer unprotected by the second hard mask to form a tunnel barrier, second magnetic materials, and a second electrode.

A magnetic memory element switchable by current injection includes a plurality of magnetic layers, at least one of the plurality of magnetic layers having a perpendicular magnetic anisotropy component and including a current-switchable magnetic moment, and at least one barrier layer formed adjacent to the plurality of magnetic layers (e.g., between two of the magnetic layers). The memory element has the switching threshold current and device impedance suitable for integration with complementary metal oxide semiconductor (CMOS) integrated circuits.

We describe the structure and method of forming a STT-MTJ MRAM cell that utilizes transfer of spin angular momentum as a mechanism for changing the magnetic moment direction of a free layer. The device includes an IrMn pinning layer, a SyAP pinned layer, a naturally oxidized, crystalline MgO tunneling barrier layer that is formed on an Ar-ion plasma smoothed surface of the pinned layer and, in one embodiment, a free layer that comprises an amorphous layer of Co₆₀Fe₂₀B₂₀. of approximately 20 angstroms thickness formed between two crystalline layers of Fe of 3 and 6 angstroms thickness respectively. The free layer is characterized by a low Gilbert damping factor and by very strong polarizing action on conduction electrons. The resulting cell has a low critical current, a high dR/R and a plurality of such cells will exhibit a low variation of both resistance and pinned layer magnetization angular dispersion.

The present invention relates generally to semiconductor fabrication and particularly to fabricating magnetic tunnel junction devices. In particular, this invention relates to a method for using the dielectric layer in tunnel junctions as an etch stop layer to eliminate electrical shorting that can result from the patterning process.

A MTJ that minimizes spin-transfer magnetization switching current (Jc) in a Spin-RAM to <1×10⁶ A/cm² is disclosed. The MTJ has a Co₆₀Fe₂₀B₂₀/MgO/Co₆₀Fe₂₀B₂₀ configuration where the CoFeB AP1 pinned and free layers are amorphous and the crystalline MgO tunnel barrier is formed by a ROX or NOX process. The capping layer preferably is a Hf/Ru composite where the lower Hf layer serves as an excellent oxygen getter material to reduce the magnetic “dead layer” at the free layer/capping layer interface and thereby increase dR/R, and lower He and Jc. The annealing temperature is lowered to about 280° C. to give a smoother CoFeB/MgO interface and a smaller offset field than with a 350° C. annealing. In a second embodiment, the AP1 layer has a CoFeB/CoFe configuration wherein the lower CoFeB layer is amorphous and the upper CoFe layer is crystalline to further improve dR/R and lower RA to ≦10 ohm/μm².

An MTJ in an MRAM array or in a TMR read head is comprised of a capping layer with a lower inter-diffusion barrier layer, an intermediate oxygen gettering layer, and an upper metal layer that contacts a top conductor. The composite capping layer is especially useful with a moderate spin polarization free layer such as a NiFe layer with a Fe content of about 17.5 to 20 atomic %. The capping layer preferably has a Ru/Ta/Ru configuration in which the lower Ru layer is about 10 to 30 Angstroms thick and the Ta layer is about 30 Angstroms thick. As a result, a high dR/R of about 40% is achieved with low magnetostriction less than about 1.0 E-6 in an MTJ in an MRAM array. Best results are obtained with an AlOx tunnel barrier layer formed by an in-situ ROX process on an 8 to 10 Angstrom thick Al layer.

A method for manufacturing a device, includes: (A) forming a first electrode layer on a substrate; (B) forming a ferroelectric layer on the first electrode layer; (C) forming a second electrode layer on the ferroelectric layer; (D) forming a mask having a predetermined pattern on the second electrode layer; (E) forming a memory element by selectively removing the first electrode layer, the ferroelectric layer, and the second electrode layer using the mask; and (F) removing the mask, where at least, the processes (D) and (E), or the processes (E) and (F) are continuously performed under a reduced pressure.

A method and system for providing a magnetic element is disclosed. The method and system include providing a pinned layer, a magnetic current confined layer, and a free layer. The pinned layer is ferromagnetic and has a first pinned layer magnetization. The magnetic current confined layer has at least one channel in an insulating matrix and resides between the pinned layer and the free layer. The channel(s) are ferromagnetic, conductive, and extend through the insulating matrix between the free layer and the pinned layer. The size(s) of the channel(s) are sufficiently small that charge carriers can give rise to ballistic magnetoresistance in the magnetic current confined layer. The free layer is ferromagnetic and has a free layer magnetization. Preferably, the method and system also include providing a second pinned layer and a nonmagnetic spacer layer between the second pinned layer and the free layer. In this aspect, the magnetic element is configured to allow the free layer magnetization to be switched using spin transfer.

A method of fabricating a magnetic tunnel junction (MTJ) device is provided. A patterned hard mask is oxidized to form a surface oxide thereon. An MTJ stack is etched in alignment with the patterned hard mask after the oxidizing of the patterned hard mask. Preferably, the MTJ stack etch recipe includes chlorine and oxygen. Etch selectivity between the hard mask and the MTJ stack is improved.

A MTJ for a spintronic device is disclosed and includes a thin composite seed layer made of at least Ta and a metal layer having fcc(111) or hcp(001) texture as in Ta/Ti/Cu to enhance perpendicular magnetic anisotropy (PMA) in an overlying laminated layer with a (CoFe/Ni)_X, (Co/NiFe)_X, (Co/NiCo)_X, (CoFe/NiFe)_X, or (CoFe/NiCo)_X composition where x is from 5 to 30. In one embodiment, a CPP-TMR spin valve has one or both of a laminated free layer and laminated reference layer with the aforementioned compositions. The MTJ includes an interfacial layer made of CoFeB, CoFeB/CoFe, or CoFe/CoFeB between each laminated structure and the tunnel barrier. The laminated layers are deposited by a low power and high Ar pressure process to avoid damaging interfaces between adjoining layers. Annealing occurs at 220° C. to 400° C. A laminated layer with high PMA may also be included in one or more layers of a spin transfer oscillator.

Methods of fabricating MTJ arrays using two orthogonal line patterning steps are described. Embodiments are described that use a self-aligned double patterning method for one or both orthogonal line patterning steps to achieve dense arrays of MTJs with feature dimensions one half of the minimum photo lithography feature size (F). In one set of embodiments, the materials and thicknesses of the stack of layers that provide the masking function are selected so that after the initial set of mask pads have been patterned, a sequence of etching steps progressively transfers the mask pad shape through the multiple mask layer and down through all of the MTJ cell layers to the form the complete MTJ pillars. In another set of embodiments, the MTJ/BE stack is patterned into parallel lines before the top electrode layer is deposited.

Fabrication methods for MRAM are described wherein any re-deposited metal on the sidewalls of the memory element pillars is cleaned before the interconnection process is begun. In embodiments the pillars are first fabricated, then a dielectric material is deposited on the pillars over the re-deposited metal on the sidewalls. The dielectric material substantially covers any exposed metal and therefore reduces sources of re-deposition during subsequent etching. Etching is then performed to remove the dielectric material from the top electrode and the sidewalls of the pillars down to at least the bottom edge of the barrier. The result is that the previously re-deposited metal that could result in an electrical short on the sidewalls of the barrier is removed. Various embodiments of the invention include ways of enhancing or optimizing the process. The bitline interconnection process proceeds after the sidewalls have been etched clean as described.

Magnetic Random Access Memory (MRAM) devices include a lower electrode and a magnetic tunnel junction on the lower electrode. The magnetic tunnel junction includes a seed layer and a tunneling barrier that is oriented in a same direction as the most closely packed plane direction of the seed layer. An oxide layer may be provided between the lower electrode and the magnetic tunnel junction. The lower electrode may be a titanium-rich TiN layer having more than 50 atomic percent titanium content. Analogous fabrication methods are also described.

A spin-transfer-torque magnetoresistive memory comprises apparatus and method of manufacturing a three terminal magnetoresistive memory element having highly conductive bottom electrodes overlaid on top of a SHE-metal layer in the regions outside of an MTJ stack. The memory cell comprises a bit line positioned adjacent to selected ones of the plurality of magnetoresistive memory elements to supply a reading current across the magnetoresistive element stack and two highly conductive bottom electrodes overlaid and electrically contacting on top of a SHE-metal layer in the outside of an MTJ region and to supply a bi-directional spin Hall effect recording current, and accordingly to switch the magnetization of the recording layer. Thus magnetization of a recording layer can be readily switched or reversed to the direction in accordance with a direction of a current along the SHE-metal layer by applying a low write current.

A method for fabricating a transducer on a substrate is described. The transducer includes an antiferromagnetic seed structure. The antiferromagnetic seed structure includes a first NiFe layer, a first multilayer including a first Ru layer, a second NiFe layer, and a second multilayer including a second Ru layer. The second multilayer, the second NiFe layer and part of the first Ru layer are removed using a first wet etch, which uses a first etchant combination to remove NiFe and in which Ru is insoluble. The second Ru layer is removed through lift-off due to etching of the second NiFe layer. A remainder of the first Ru layer is removed through a second wet etch, which uses a second etchant combination to remove Ru. A remaining portion of the first multilayer and the first NiFe layer are removed through a third etch, which uses a third etchant combination that removes NiFe.