162 results about "Electrical Shorting" patented technology

The present invention relates generally to semiconductor fabrication and particularly to fabricating magnetic tunnel junction devices. In particular, this invention relates to a method for using the dielectric layer in tunnel junctions as an etch stop layer to eliminate electrical shorting that can result from the patterning process.

An enhanced inductive coil design for use in data storage magnetic disk drives with areal density over 35 Gb / in2, features a double wound twin coil that is able to achieve a yoke length of 15 μm or less by reducing the insulation spacing between the two coils. The coil further presents improved reliability by reducing the possibility of occurrence of electrical shorting. The coil is made by forming two interleafing conductors on the same layer with a demesne process. A tri-level process is implemented in the layout of the first conductor to ensure that the coil width and spacing are uniform and even, in order for the second conductor to be wound therebetween. A conformal dielectric layer of approximately 0.1 to 0.2 μm in thickness is deposited between the two conductors and serves as insulation. The two conductors are formed by a copper seed layer plating process that eliminates potential damage to the conductors during production.

A filled-gap magnetic recording head is provided comprising a flat or cylindrical contour head having a row of magnetic transducers in a gap region disposed between a rowbar substrate and a closure. The gap region is intentionally recessed to have a predetermined recess profile below a tape support surface. An electrical insulation layer is deposited on the tape support surface and on the recess profile of the gap region. The insulation layer prevents electrical shorting between the magnetic transducers and other conductive elements in the gap due to accumulations of conductive debris from the magnetic recording tape. A method of making the filled-gap magnetic recording head by intentionally recessing the gap region, cleaning the recessed profile and depositing an insulator layer is provided.

The disclosed electrostatic precipitator cartridge for a tower air cleaner in accord with the present invention is low-cost, because constructed of injected molded plastics material and stamped and extruded metal components. It is easy to clean, not only because it's constitutive metal parts and plastic components are machine washable but also because the cartridge as a whole is machine washable, the pieces and components are designed and arranged to prevent intracartridge fluid buildup or retention after washing, thereby eliminating any electrical shorting or arcing or other undesirable phenomena resulting therefrom that could interfere with the operation of the electrostatic filter cartridge. It is mechanically stable and has high particulate collection efficiency because it's ionizer bars have a predetermined preferably air foil shape that provides improved ionization efficiency and that imparts improved torsion stability rendering it possible to provide taller electrostatic filter cartridges and / or greater cleaning power.

This invention is about a method to make magnetic random access memory with small footprint directly on CMOS VIA with a self-aligned etching process. The process schemes of the method proceeds as: (1) Etch MTJ and BE using one or more of RIE and / or IBE processes with Ta as hard mask; (2) Etch BE using one or more of RIE and / or IBE processes with Ta & sidewall protection layer on MTJ as hard mask; and (3) Etch a part of MTJ and BE using one or more of RIE and / or IBE processes with Ta & sidewall protection layer on top portion of MTJ as hard mask. All the three schemes lead the BE to be self-aligned to MTJ cells, the photo overlay margin is not necessary and circuits could be made extremely small with lower manufacturing cost; The invention also provides schemes to prevent the electrical shorting across the tunnel barrier layer. Through trimming and sidewall protection deposition process, device performance and electrical / magnetic properties could be greatly improved.

A method for reducing shunt-related defects is described for hydrogenated amorphous silicon (a-Si:H) thin film photovoltaic modules with thin active a-Si:H absorber as required by building integrated photovoltaic windows and sun-roofs with adequate transmission of sunlight. Without shunt-passivation, p-i-n type large area photovoltaic modules with very thin a-Si:H i-layer will suffer excessive performance, yield, and reliability losses due to electrical shorting through i-layer defects. Wide-bandgap a-Si:H based alloy films of sufficient resistivity are deposed between the active solar cell and the conductive back electrode to provide a barrier to leakage current flow. Such a-Si:H based barrier films of high optical transparency are dummy films that do not directly contribute to energy conversion. The shunt-passivation films are entirely produced by the same conventional manufacturing process for a-Si:H photovoltaic devices without invoking complicated or exotic materials or procedures proposed in prior arts.

<heading lvl="0">Abstract of Disclosure< / heading> A method of making a double layer capacitor consists of the steps of: impregnating each of a plurality of carbon preforms with a metal; forming a plurality of current collector foils, each of the plurality of current collector foils having a tab portion and a paddle portion; forming a plurality of electrodes by positioning one of the plurality of carbon preforms against respective paddle portions of each of the plurality of current collector foils, wherein each of the plurality of electrodes comprises one of the plurality of current collector foils and one of the plurality of carbon preforms; stacking each of the plurality of electrodes such that tab portions of adjacent ones of the plurality of current collector foils are offset, thereby forming an electrode stack; interposing respective porous separator portions between each of the plurality of electrodes, wherein the porous separator portions function as electrical insulators between the adjacent ones of the plurality of electrodes preventing electrical shorting against each other; applying a modest constant pressure against the electrode stack; saturating the electrode stack with an electrolytic solution; and maintaining the electrode stack immersed within the electrolytic solution.

Disclosed herein is a battery cartridge-connecting system for battery modules, comprising: bus bars, each of which includes a plate-shaped bar body, coupling parts, and electrical connection parts; a base plate, to which the bus bars are easily mounted; and a printed circuit board (PCB), which is easily coupled to the bus bars and is mounted to the base plate in a compact structure. The present invention also provides a battery module and a medium- or large-sized battery system including the battery cartridge-connecting system. According to the present invention, the battery cartridge-connecting system easily accomplishes the electrical connection and the mechanical coupling in the compact-structured battery module or battery system. In addition, the battery cartridge-connection system has excellent electrical characteristics, such as electric resistance at the connected parts, after the electrical connection is completed, and excellent mechanical strength to external impacts or vibrations after the mechanical coupling is completed. Furthermore, the battery cartridge-connecting system prevents a risk of an engineer or a user being exposed to the electrical short circuits when the battery module or the battery system is manufactured or when the battery module or the battery system is repaired.

An MTJ cell without footings and free from electrical short-circuits across a tunneling barrier layer is formed by using a Ta hard mask layer and a combination of etches. A first etch patterns the Ta hard mask, while a second etch uses O2 applied in a single high power process at two successive different power levels. A first power level of between approximately 200 W and 500 W removes BARC, photoresist and Ta residue from the first etch, the second power level, between approximately 400 W and 600 W continues an etch of the stack layers and forms a protective oxide around the etched sides of the stack. Finally, an etch using a carbon, hydrogen and oxygen gas completes the etch while the oxide layer protects the cell from short-circuits across the lateral edges of the barrier layer.

A lapping method utilizing textured and conditioned lapping plates most suitable for finishing magnetic heads resulting in improved surface quality, less sensitivity to electrical shorts due to smears, and reduced surface height difference between the head elements exposed at the slider air bearing surface. A rough lapping phase is followed by a polishing phase that maintains the same mechanical motion between the work piece and lapping plate but utilizes only the lapping plate without abrasives of any kind to polish the work piece surface, and to clean up any deep textured marks resulting from the diamond slurry phase. A conductive liquid is utilized to provide lubrication and to minimize static charge.

A self-aligned gate cap dielectric can be employed to form a self-aligned contact to a diffusion region, while preventing electrical short with a gate conductor due to overlay variations. In one embodiment, an electroplatable or electrolessly platable metal is selectively deposited on conductive materials in a gate electrode, while the metal is not deposited on dielectric surfaces. The metal portion on top of the gate electrode is converted into a gate cap dielectric including the metal and oxygen. In another embodiment, a self-assembling monolayer is formed on dielectric surfaces, while exposing metallic top surfaces of a gate electrode. A gate cap dielectric including a dielectric oxide is formed on areas not covered by the self-assembling monolayer. The gate cap dielectric functions as an etch-stop structure during formation of a via hole, so that electrical shorting between a contact via structure formed therein and the gate electrode is avoided.

A system (10) for establishing bypass of a failed battery cell (18) includes a failed cell sensor (26) which on sensing a failed cell generates an electric signal that destroys clamping relation of two retaining wire spools (24) to release retaining means (14,16). Such release enables a unitary plunger assembly (28) to be moved by a spring (49) to position a cylindrical pin contact (52) in electrical shorting relation to the first and second electrodes (57,58) connected across the cell (18).

Disclosed herein is a secondary battery module constructed approximately in a rectangular parallelepiped structure. The battery module includes a pair of side members (right and left side members) having pluralities of grooves formed at the inside surfaces thereof such that the sides of unit cells are securely fitted in the grooves and at least one connection member integrally formed with the side members such that the side members are spaced apart from each other by the width of the unit cells while the grooves of the side members face each other. A medium- or large-sized battery system is manufactured using one or more secondary battery module. The secondary battery module allows a plurality of unit cells to be mounted in the battery module with high density. Consequently, the total size of the battery system can be considerably reduced, and the electrical connection between the electrodes is highly stable. Furthermore, a risk of an engineer or a user being exposed to the electrical short-circuits is minimized, and a risk of electrical short-circuits due to external forces is greatly reduced.

The disclosed invention provides a structure and method for providing a high lateral voltage resistance between the electrical networks, sharing a lateral plane, of conductive elements (e.g., having different high voltage potentials) comprising a coupler. In one embodiment, an integrated coupler providing a high lateral voltage resistance comprises a primary conductive element and a secondary conductive element. An isolating material is laterally configured between the electrical network of the primary conductive element and an electrical network of the secondary conductive element. The isolating material may comprise a low-k dielectric layer and prevents any lateral barrier layers (e.g., etch stop layers, diffusion barrier layers, etc.) from extending between the first conductive element and the electrical network of the second conductive element. The structure therefore provides a galvanically isolated integrated coupler which avoids electrical shorting between circuits (e.g., at barrier layers) resulting in an improved high voltage resistance.

An electrical shorting system includes an electrical switch having a first terminal, a second terminal, and a switching terminal. The electrical shorting system also includes a housing, a first contact in electrical communication with the first terminal of the electrical switch and supported by the housing, and a second contact in electrical communication with the second terminal of the electrical switch and supported by the housing. The electrical switch may be in a closed state in which the first contact is shorted with the second contact through the electrical switch, and when a voltage is applied to the switching terminal, the electrical switch is placed in an open state that impedes current flow through the electrical switch between the first contact and the second contact.

In one illustrative example disclosed, a method for use in making a magnetic head involves forming a thermal-assist heater for the magnetic head; forming a plurality of coil layers of a write coil using a damascene process; and simultaneously forming an electrical connection to the thermal-assist heater in the same damascene process used to form the write coil. Advantageously, fabrication steps are reduced using a parallel process that provides for relatively small dimensions and reduces the possibility of electrical shorting. The method may be alternatively used to form an electrical connection to any other suitable electrical device for the magnetic head, such as an electrical lapping guide (ELG) or other component.

In one illustrative example disclosed, a method for use in making a magnetic head involves forming a thermal-assist heater for the magnetic head; forming a plurality of coil layers of a write coil using a damascene process; and simultaneously forming an electrical connection to the thermal-assist heater in the same damascene process used to form the write coil. Advantageously, fabrication steps are reduced using a parallel process that provides for relatively small dimensions and reduces the possibility of electrical shorting. The method may be alternatively used to form an electrical connection to any other suitable electrical device for the magnetic head, such as an electrical lapping guide (ELG) or other component.

The present invention relates generally to semiconductor fabrication and particularly to fabricating magnetic tunnel junction devices. In particular, this invention relates to a method for using the dielectric layer in tunnel junctions as an etch stop layer to eliminate electrical shorting that can result from the patterning process.

Methods for use in forming current-perpendicular-to-the-planes (CPP) type sensors, including CPP giant magnetoresistance (GMR) type and CPP magnetic tunnel junction (MTJ) type sensors are disclosed. In one particular example, a plurality of CPP type sensor layers are formed over a wafer and a mask without undercuts is formed over the plurality of CPP type sensor layers in a central region. With the mask without undercuts in place, an ion milling process is started to remove CPP type sensor layer materials left exposed by the mask without undercuts in end regions which surround the central region. The ion milling process is stopped at or near a spacer layer of the CPP type sensor layers. Insulator materials are then deposited in the end regions where the CPP type sensor layer materials were removed, followed by hard bias materials over the insulator materials. The mask without undercuts is then removed through use of a chemical-mechanical polishing (CMP) assisted lift-off process, which also planarizes the top surface. Typical sensor techniques of the art are then performed to complete manufacture of the CPP type sensor. Using the mask without undercuts enables the removal of a freelayer of the plurality of CPP type sensor layers down to the spacer layer or beyond to form the CPP type sensor with sharp and steep sidewalls which is not possible with conventional mask structures. The act of stopping the ion milling process at or near the spacer layer reduces a likelihood of electrical shorting around side edges of the spacer layer. This unique combination thereby results in improved CPP type sensor performance through improved amplitude and stability.

Electronic components on a substrate may be shielded using electromagnetic shielding structures. Insulating materials may be used to provide structural support and to help prevent electrical shorting between conductive materials and the components. The shielding structures may include compartments formed using metal fences that surround selected components or by injection molding plastic. The shielding structures may be formed using metal foil wrapped over the components and the substrate. Electronic components may be tested using test posts or traces to identify components that are faulty. The test posts or traces may be deposited on the substrate and may be used to convey test signals between test equipment and the components. After successful testing, the test posts may be permanently shielded. Alternatively, temporary shielding structures may be used to allow testing of individual components before an electronic device is fully assembled.

A first patterned contact layer, for example a gate electrode, is formed over an insulative substrate. Insulating and functional layers are formed at least over the first patterned contact layer. A second patterned contact layer, for example source / drain electrodes, is formed over the functional layer. Insulative material is then selectively deposited over at least a portion of the second patterned contact layer to form first and second wall structures such that at least a portion of the second patterned contact layer is exposed, the first and second wall structures defining a well therebetween. Electrically conductive or semiconductive material is deposited within the well, for example by jet-printing, such that the first and second wall structures confine the conductive or semiconductive material and prevent spreading and electrical shorting to adjacent devices. The conductive or semiconductive material is in electrical contact with the exposed portion of the second patterned contact layer to form, e.g., an operative transistor.

An electrified vehicle has first and second DC buses and a chassis ground. A leakage detector has a detector switch and detector resistor in series between the first bus and chassis ground. A voltage measured across the detector resistor is proportional to a leakage resistance between the second bus and chassis. An inverter has a plurality of phase legs, each having first and second phase switches coupled between the buses. An AC traction motor has phases coupled to the phase legs. An inverter control circuit receives data messages having a predetermined latency period from the detector identifying a measured leakage resistance. Switching events are detected during which a phase switch is closed for a duration greater than the latency period. An electrical short is indicated if the measured leakage resistance in a data message received during a detected switching event is less than a predetermined threshold.

An etch resistant liner covering sidewalls of a transistor gate stack and along a portion of the substrate at a base of the transistor gate stack. The liner prevents silicide formation on the sidewalls of the gate stack, which may produce electrical shorting, and determines the location of silicide formation within source and drain regions within the substrate at the base of the transistor gate stack. The liner also covers a resistor gate stack preventing silicide formation within or adjacent to the resistor gate stack.

The method of process control is for a Hall-Héroult process of aluminum production from alumina ore in an industrial potline. The method includes measuring an array of sampled potline data including a plurality of cell voltages (V) and a plurality of line amperages (A) at a plurality of time points. The method also includes calculating a predicted voltage (PV) for each cell voltage and line amperage in the array. The method further includes controlling a plurality of alumina ore feed rates and a plurality of pot voltage settings based upon the predicted voltages. The method also includes calculating a plurality of bath temperatures based upon the predicted voltages. The PV variable is preferably used in an automated control environment. The PV variable is also preferably used to monitor cell noise levels, operating temperature, metal pad roll, and oscillatory electrical shorting events.