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55results about How to "Voltage change" patented technology

Electrooptic device, driving circuit, and electronic device

A driving circuit of an electrooptic device includes: a plurality of scanning lines; a plurality of data lines; first and second capacitor lines; a common electrode; pixels; a scanning-line driving circuit; a capacitor-line driving circuit; and a data-line driving circuit. The pixels each include: a pixel switching element; a pixel capacitor disposed between the pixel switching element and the common electrode; and a storage capacitor. When the one scanning line is selected, the capacitor-line driving circuit shifts the voltage of a first (or second) capacitor line corresponding to one scanning line to one of higher and lower levels from a predetermined voltage by a predetermined value, and holds the predetermined voltage after a scanning line apart from the one scanning line by a predetermined number of lines is selected until the one scanning line is selected again.
Owner:JAPAN DISPLAY WEST

Scan driver and flat panel display using the same

A flat panel display (FPD) includes: a timing controller configured to supply a mode control signal and a scan control signal; a plurality of pixels coupled to a plurality of scan lines and a plurality of data lines; a data driver for supplying a plurality of data signals to the data lines, and a scan driver coupled to the scan lines and including a plurality of scan integrated circuits (ICs), each of the scan ICs being configured to supply a plurality of scan signals to corresponding ones of the scan lines, wherein the timing controller is configured to select of the scan ICs in accordance with the mode control signal and wherein the timing controller is further configured to control a corresponding scan signal of the scan signals to be supplied to one of the scan lines coupled to the scan IC selected in accordance with the scan control signal.
Owner:SAMSUNG DISPLAY CO LTD

Pressure sensor device

A pressure sensor device includes a substrate having a first section and a second section being adjacent to the first section and thinner than the first section, a piezoelectric film having flexibility and disposed on the second section, an upper electrode formed on the piezoelectric film and including a center electrode disposed at a substantially center of the second section in plan view, and a peripheral electrode disposed apart from the center electrode so as to surround the center electrode, a lower electrode formed between the second section and the piezoelectric film and disposed so as to face the upper electrode, and a detection circuit including a differential circuit electrically connected to the center electrode and the peripheral electrode, and the detection circuit detects a difference between a voltage caused between the center electrode and the lower electrode in response to the piezoelectric film being distorted, and a voltage caused between the peripheral electrode and the lower electrode in response to the piezoelectric film being distorted.
Owner:SEIKO EPSON CORP

Semiconductor memory device with improved data retention characteristics

Conductive lines constituting word lines of memory cells and conductive lines constituting memory cell plate electrodes are formed in the same interconnecting layer in a memory device including a plurality of memory cells each including a capacitor for storing data in an electrical charge form. By forming the capacitors of the memory cells into a planar capacitor configuration, a step due to the capacitors is removed. Thus, a dynamic semiconductor memory device can be formed through CMOS process, and a dynamic semiconductor memory device suitable for merging with logic is achieved. Data of 1 bit is stored by two memory cells, and data can be reliably stored even if the capacitance value of the memory cell is reduced due to the planar type capacitor.
Owner:RENESAS ELECTRONICS CORP

Logic circuit, semiconductor device, electronic component, and electronic device

The drive capability of a logic circuit is improved. The logic circuit includes a first output node, a dynamic logic circuit, a diode-connected first transistor, and a capacitor. The dynamic logic circuit includes a second output node and a plurality of second transistors forming and evaluation circuit. The first transistor and the plurality of second transistors all have one of an n-type conductivity and a p-type conductivity. One terminal of the capacitor is electrically connected to the first output node. The other terminal of the capacitor is electrically connected to the second output node. A first terminal of the first transistor is electrically connected to the first output node. A first voltage is input to a second terminal of the first transistor. The voltage of the first output node is changed by a voltage applied to a back gate of the first transistor.
Owner:SEMICON ENERGY LAB CO LTD

Pixel circuit

ActiveUS20210049959A1Voltage changePreventing and reducing flickerStatic indicating devicesEngineeringData lines
A pixel circuit includes: a main circuit including: a driving transistor that includes a gate terminal connected to a first node, a first terminal connected to a second node, and a second terminal connected to a third node; and an organic light-emitting element connected to the driving transistor and configured to control the organic light-emitting element by controlling a driving current corresponding to a data signal applied via a data line to flow into the organic light-emitting element; and a sub circuit including: a first compensation transistor that includes a gate terminal configured to receive a first gate signal, a first terminal connected to the first node, and a second terminal connected to a fourth node; and a second compensation transistor that includes a gate terminal configured to receive a second gate signal, a first terminal connected to the fourth node, and a second terminal connected to the third node.
Owner:SAMSUNG DISPLAY CO LTD

Liquid crystal display device having a black matrix with a specific resistance

A first substrate, a second substrate opposing to the first substrate, and liquid crystal provided in a space between the first substrate and second substrate are provided to an IPS mode liquid crystal display. A plurality of gate lines and a plurality of drain lines, thin film transistors, pixel electrodes, and common electrodes are formed on a transparent substrate in a first substrate. Each of the thin film transistors is provided in a vicinity of the intersection of the gate line and drain line. Each of the pixel electrodes is formed within a pixel region enclosed with an adjacent pair of the gate lines and an adjacent pair of the drain lines. Each of the common electrodes develops an electric field within each of the pixel regions between the pixel electrode and itself. The second substrate includes color layers provided for each of the pixel regions. The color layers are spaced apart from the gate lines and drain lines when seen on a plane.
Owner:GOLD CHARM LTD

Battery pack charging control method and charging assembly

The present invention provides a battery pack charging control method, which comprises the following steps: during the charging process of a battery pack, each battery voltage and / or the voltage difference between batteries to be balanced in the battery pack are separately compared with corresponding thresholds, if at least one battery voltage reaches the corresponding threshold voltage and / or the voltage difference between the batteries to be balanced reaches the corresponding voltage difference threshold, an equilibrium current is started for discharging of the battery which reaches the corresponding threshold voltage, or for discharging of the high-voltage battery which reaches the voltage difference threshold; during the discharging process of the equilibrium current, a charging switch is controlled to be alternately on and off to reduce the average current of charging; or the voltage drop of the charging switch is increased to enable the charging switch to work in a linear mode, in order to reduce the charging current until the battery voltage decreases to be lower than the corresponding threshold voltage and / or the voltage difference between the batteries to be balanced is reduced to the corresponding voltage difference threshold.
Owner:JOULWATT TECH INC LTD

Electric power supply unit having improved output voltage response

The power supply unit is provided with a power supply circuit adapted to generate an output voltage in accord with an instruction voltage, an output condenser Co connected to the output end of the power supply circuit, and an auxiliary output voltage setting circuit adapted to compare the instruction voltage and the output voltage and to cause the output condenser to discharge its electric charge when the instruction voltage becomes lower than the output voltage. Because of the auxiliary output voltage setting circuit, the power supply circuit quickly generates an output voltage in accord with the instruction voltage if the instruction voltage is lowered.
Owner:ROHM CO LTD

Multi-anode electric field synthesis device

The invention provides a multi-anode electric field synthesis device which comprises an electrolytic tank, an electrolytic tank cover, a plurality of anodes and a plurality of cathodes. The anodes andthe cathodes are arranged in the electrolytic tank, an electrolytic power supply is connected between the anodes and the cathodes, the electrolytic tank cover is located at the top of the electrolytic tank and detachably mounted on the electrolytic tank, and the plurality of anodes are connected in parallel to a positive electrode of a power supply through wires; and a plurality of tracks are arranged on the electrolytic tank cover, and the plurality of anodes are movably arranged on the tracks. A plurality of metal anodes are adopted, different metals can be dissolved in a same solution through parallel electric fields, and dissolved metal ions are reduced into nanoparticles through an electrolyte solution (containing reducing substances); and meanwhile, the carbon rod cathodes are stripped into graphene to be dispersed into the solution, so that the multi-metal nanoparticles are loaded, and the multi-metal / graphene composite material is synthesized.
Owner:山西师范大学

High-density EEPROM arrays having parallel-connected common-floating-gate NFET and PFET as memory cell

A memory array includes an N×M array of memory cells, each memory cell having a first transistor connected to a first terminal and a second transistor connected in parallel to the first transistor and a second terminal, where the first and second transistors share a common floating gate and a common output node. Each memory cell further includes an access transistor connected in series to the common output node and a low voltage terminal, the access transistor configured to trigger hot-carrier injection to the common floating gate to change a voltage of the common floating gate. The first transistor is an n-type transistor and the second transistor is a p-type transistor.
Owner:IBM CORP
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