A computer
system includes a South bridge logic that connects an expansion
bus to one or more secondary expansion busses and
peripheral devices. The South bridge logic includes internal control devices that are targets for masters on the expansion
bus. The target devices couple to the expansion
bus through a common expansion target interface, which monitors and translates master cycles on the expansion bus on behalf of the target devices. The South bridge includes an ACPI /
power management logic capable of supporting a Device Idle mode in which selected I / O device may be placed in a low power state. To prevent cycles from being run to a device in a low power state, the ACPI /
power management includes status registers that are used to determine when a device in low
power mode is the target of an expansion bus cycle. If such a cycle occurs, the cycle is intercepted and an SMI
signal is transmitted to the CPU. In addition, the target interface responds to the master by asserting a retry
signal. When the transaction is retried, the cycle is passed to the target, which responds with an
invalid data signal. The CPU by this time, or at some subsequent time realizes that the target was asleep based upon
processing of the SMI signal. The CPU then either re-executes the cycle when the device is removed form the low power state, or else simply rejects the
invalid data.