146 results about "Memory refresh" patented technology

A memory system is disclosed. The memory system includes a memory controller coupled to one or more memory modules, at least one of the memory modules including a buffer. The memory controller is configured to convey a command to at least one of the memory modules in response to detecting that no memory requests addressed to the at least one of the memory modules have been received during a specified window of time. In response to the command, the buffer of the at least one of the memory modules is configured to enter a reduced power state. The specified window of time may be either a specified number of memory refresh intervals or buffer sync intervals. The memory controller maintains a count of memory refresh or buffer sync intervals.

A memory controller to implement targeted refreshes of potential victim rows of a row hammer event. In an embodiment, the memory controller receives an indication that a specific row of a memory device is experiencing repeated accesses which threaten the integrity of data in one or more victim rows physically adjacent to the specific row. The memory controller accesses default offset information in the absence of address map information which specifies an offset between physically adjacent rows of the memory device. In another embodiment, the memory controller determines addresses for potential victim rows based on the default offset information. In response to the received indication of the row hammer event, the memory controller sends for each of the determined plurality of addresses a respective command to the memory device, where the commands are for the memory device to perform targeted refreshes of potential victim rows.

The optimization of a refresh cycle is carried out in harmony with the error occurrence state in the memory with the presence of a normal patrol controlling section controlling a normal patrol operation that patrols the memory; an additional patrol controlling section controlling an additional patrol operation that patrols, if a first error in the memory is detected during the normal patrol operation, an error occurring area in which the first error occurs and which is included in the memory; a measuring section (15) measuring, if a second error is detected in the error occurring area during the additional patrol operation, an error frequency representing information of error in the error occurring area; and a refresh cycle adjusting section adjusting the refresh cycle in accordance with the error frequency measured by the measuring section.

Power consumption of a mobile communication device is reduced by disabling refreshing of unused portions of DRAM. DRAM includes multiple separately refreshable memory refresh ranges (MRRs). A memory refresh manager (MRM) within the device's operating system identifies ranges of virtual memory that will not be used during subsequent sleep mode operation. The MRM remaps virtual to physical memory space to conglomerate the physical memory pages (associated with virtual memory that will not be used) in certain MRRs such that the contents of entire MRRs need not be maintained in sleep mode. Information in any remapped physical page that needs to be maintained during sleep mode is copied so that it resides at the same virtual address after the remapping as before. Other software operates in virtual memory space and is not affected by the remapping. Refreshing of the certain MRRs is then disabled for sleep mode, thereby reducing power consumption.

A Programmable Logic Device (PLD) is provided with configuration memory cells displaying a superior soft error immunity by combating single event upsets (SEUs) as the configuration memory cells are regularly refreshed from non-volatile storage depending on the rate SEUs may occur. Circuitry on the PLD uses a programmable timer to set a refresh rate for the configuration memory cells. Because an SEU which erases the state of a small sized memory cell due to collisions with cosmic particles may take some time to cause a functional failure, periodic refreshing will prevent the functional failure. The configuration cells can be DRAM cells which occupy significantly less space than the SRAM cells. Refresh circuitry typically provided for DRAM cells is reduced by using the programming circuitry of the PLD. Data in the configuration cells of the PLD are reloaded from either external or internal soft-error immune non-volatile memory.

Memory interface for multi-CPU system provides predefined time slots in which each CPU may access an external memory. The time slot assigned to each CPU may be defined according to the expected memory requirements of the CPU. In this way, each CPU is guaranteed to have a certain amount of dedicated bandwidth to the external memory. The predefined time slots also allow the latency of the system to be known, which is useful for real-time oriented applications. Moreover, each CPU may use its own clock during its allotted time slot to control the external memory, thus accommodating various clock domains in the system. Memory refresh and data protection functions are also provided. This Abstract is provided to comply with rules requiring an Abstract that allows a searcher or other reader to quickly ascertain subject matter of the technical disclosure. This Abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

A dynamic random access memory solves long-existing tight pitch layout problems using a multiple-dimensional bit line structure. Improvement in decoder design further reduces total area of this memory. A novel memory access procedure provides the capability to make internal memory refresh completely invisible to external users. By use of such memory architecture, higher performance DRAM can be realized without degrading memory density. The requirements for system support are also simplified significantly.

A memory devices provide signals indicating when refresh operations are complete. The signals from a number of memory devices can be combined, such as by Oring, to provide a refresh complete signal to a power management controller. Dynamic factors can affect the refresh operation and the memory may be refreshed without restoring the entire system to a high power state. The time required to perform a refresh operation can be determined dynamically, allowing the system to be returned to a low power state as soon as refresh is complete. Ambient temperatures can be monitored to dynamically determine when to perform a refresh operation.

A memory refresh requestor, a memory request interpreter, a cache memory, and a cache controller on a single chip. The cache controller configured to receive a memory access request, the memory access request for a memory address range in the cache memory, detect that the cache memory located at the memory address range is available, and send the memory access request to the memory request interpreter when the memory address range is available. The memory request interpreter configured to receive the memory access request from the cache controller, determine if the memory access request is a request to refresh a contents of the memory address range, and refresh data in the memory address range when the memory access request is a request to refresh memory.

For use with a memory controller in a data processor that is capable of executing memory refresh requests to refresh a memory of the data processor, an apparatus and method is disclosed for scheduling execution of the memory refresh requests. The apparatus comprises a periodic memory refresh hint unit that is capable of sending to the memory controller a data signal that comprises a periodic memory refresh hint. The periodic memory refresh hint informs the memory controller of an optimal time for a memory refresh to occur. The memory controller may immediately execute a memory refresh request when it arrives or delay the execution of the memory refresh request until a more opportune time. This feature enables the memory controller to reduce memory access latency in scheduling memory transactions.

A dynamic random access memory solves long-existing tight pitch layout problems using a multiple-dimensional bit line structure. Improvement in decoder design further reduces total area of this memory. A novel memory access procedure provides the capability to make internal memory refresh completely invisible to external users. By use of such memory architecture, higher performance DRAM can be realized without degrading memory density. The requirements for system support are also simplified significantly.

A dynamic memory refresh controller includes a first in first out (FIFO) memory, a scheduler, a refresh control unit, and a signal generator. The FIFO memory stores and manages requests from a master device. The scheduler reorders the requests from the master device based on priorities assigned to the master device or provides information about following requests. The refresh control unit determines a refresh timing of the dynamic memory based on the existence of the following requests and an idle state of banks constituting the dynamic memory. Accordingly, the dynamic memory refresh controller may maximize a refresh trigger interval by changing the management order of the requests from the master device based on the priority of the response latency.

A method, an apparatus, and a computer program are provided to control refreshes in Extreme Data Rate (XDR™) memory systems. XDR™ memory systems employ calibrations to ensure the precise transmission of data. During calibrations, memory refreshes can occur; however, these refreshes can interfere with calibration streams. Therefore, to alleviate collisions and interferences, refreshes are deferred to periods where no calibrations are taking place. The number of deferred refreshes is also tracked such that the overall loss of refreshes is prevented.

A delay device is added to the addressing and refreshing circuitry of a DRAM array including DRAM devices less volatile than conventional DRAM devices and, thus, need not be refreshed as often. The delay device is connected to intercept refresh signals generated by a conventional DRAM refresh controller and initiates a refresh cycle after disregarding a predetermined number of refresh signals generated by the refresh controller whose total duration equals the interval by which the less volatile DRAM devices must be refreshed. The delay device also is adapted to power off circuitry needed to address the DRAM devices when the DRAM devices are not being refreshed or otherwise accessed. Additional circuitry is added to selectively power on only specific addressing devices actually needed to address those certain portions of the array being refreshed at that time.

Disclosed is a dual inline memory module with temperature-sensing scenario modes. A plurality of volatile memory components and an EEPROM component are disposed on a module board. A plurality of LED components and a scenario-lighting controller are disposed at a radiant side of the module board. A light bar is located at the radiant side of the module board without direct installing relationship. A plurality of clamping-type heat spreaders are fastened to one another in a manner that the light bar is tightly clamped. Therein, the power of the scenario-lighting controller component is shared and linked with the power supply system of the LED components and the signals of the scenario-lighting controller component are shared and linked with the signal connection system of the EEPROM component. Accordingly, the lighting scenario performances controlled by the scenario-lighting controller accord with the sensing temperatures to adjust memory refreshing frequencies to avoid any incorrect performance caused by sensed temperature differences.

One embodiment provides a semiconductor device including a plurality of multi-bit memory cells, a first temperature balance sensor, and a circuit. Each of the plurality of multi-bit memory cells can be programmed to each of two or more states. The circuit compares the first signal from the first temperature budget sensor with the first reference signal to obtain a first comparison result. The circuit refreshes a plurality of multi-bit storage devices according to the first comparison result.