A high speed dram architecture with uniform access latency

Abstract

A Dynamic Random Access Memory (DRAM) performs read, write, and refresh operations. The DRAM includes a plurality of sub-arrays, each having a plurality of memory cells, each of which is coupled with a complementary bit line pair and a word line. The DRAM further includes a word line enable device for asserting a selected one of the word lines and a column select device for asserting a selected one of the bit line pairs. A timing circuit is provided for controlling the word line enable device, the column select device, and the read, write, and refresh operations in response to a word line timing pulse. The read, write, and refresh operation are performed in the same amount of time.

Description

[0001] This application is a divisional application of the national phase entry application 01812427.5 of the international application PCT / CA01 / 00949 filed on June 29, 2001, requiring Canadian application 2313954 filed on July 7, 2000 and Priority of US application 60 / 216679. technical field [0002] The present invention relates generally to high speed DRAM structures and, more particularly, to the timing of read, write and refresh operations. Background of the invention [0003] Traditionally, commodity designs for dynamic random access memory (DRAM) have focused less on high storage performance and more on achieving low cost-per-bit through higher overall bit density. The reason is that the cell capacity of the two-dimensional memory array increases proportionally to the square of the size, and the additional area of ​​the bit line sense amplifier, word line driver, and row address (or x address) and column address (or y address) decoder Grows proportionally to size. T...

AI Technical Summary

Problems solved by technology

However, the main disadvantage of this scheme is that compared with conventional DRAM designs, the bit density in the DRAM array is greatly reduced due to doubling the number of access transistors and bit lines per memory cell.

Moreover, such systems also use an open bitline structure, which is undesirable because the sensitivity does not match the noise coupling of the bitline pair

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