187results about "Reconfigurable analogue/digital converters" patented technology

Provided is a current control circuit. A current control circuit may include a clock sensing unit configured to generate a control signal according to one or more frequencies based on a plurality of clock signals, and a current scaling unit configured to scale a bias current according to the control signal. The current control circuit according to example embodiments may dynamically control a bias current according to one or more frequencies based on a plurality of clock signals so that power consumption of an analog-to-digital converter (ADC) and the semiconductor device including the ADC, which require various operating frequencies, may be improved.

An ADC circuit includes multiple comparators and a controller coupled to the comparators. Each of the comparators is operative to generate an output indicative of a difference between a first signal representative of an input signal applied to the ADC circuit and a corresponding reference signal. The controller is operative to perform at least one of: (i) activating a subset of the comparators during a given sample period being; and (ii) controlling levels of the corresponding reference signals of the comparators as a function of a level of the input signal. A number of active comparators during the given sample period is no greater than one less than a number of regions into which the input signal is quantized.

A reconfigurable ADC includes a plurality of reconfigurable blocks for allowing the ADC to provide a plurality of architectures. In one embodiment, the ADC can be configured to operate in a pipeline mode and a sigma-delta mode. This arrangement provides an ADC having a relatively large range of bandwidth and resolution.

A variable resolution analog-to-digital converter includes a sample-and-hold circuit including a plurality of sample-and-hold units which are connected in parallel and selectively activated corresponding to a required resolution to sample and hold an analog input signal, a plurality of conversion stages connected in cascade to an output of the sample-and-hold circuit to convert an output signal of the sample-and-hold circuit to a plurality of bit signals, and a synthesis circuit to synthesize the bit signals, to generate a digital output signal.

Various apparatuses, methods and systems for a multi-mode DAC with selectable output range, granularity and offset and controlled slew rate are disclosed herein. For example, some embodiments of the present invention provide an apparatus for supplying a reference signal, including a digital-to-analog converter, a counter and a clock. The digital-to-analog converter has a digital input and an analog output that supplies a reference signal based on the digital input. The counter has a digital control word input, a clock input, a clock enable output and a count output connected to the digital input of the digital-to-analog converter. The counter is adapted to assert the clock enable output when the digital control word input requests an output count that is different from an actual count at the count output of the counter. The clock has an enable input connected to the clock enable output of the counter and a clock output connected to the clock input of the counter. The clock is adapted to produce clock pulses on the clock output while the enable input is asserted.