A
class D amplifier uses a summation of two or more PWM output stages to achieve an increased
dynamic range and improved
linearity for any given
clock operating speed. The
amplifier accepts a
digital data stream as its input, such as from a compact disk, or other compatible media, at a
data rate, Fa, that could be 44.1 kHz, 96 kHz, or any other rate appropriate for audio data. In the preferred embodiment, the input audio
data resolution, N bits, would be split into two data samples, of J and K. Internal
switching frequency, Fs, switches the PWM with an over sampling factor M, where Fs=M*Fa. The
time resolution of the PWM is determined by a precision oscillator that operates at Fc=Fs*(max(J,K)-log2(+1). The J most significant bits would be routed to a power PWM stage operated at a
DC voltage of VHI. The K least significant bits are routed to a
finesse PWM stage operated at a
DC voltage of VLO. The ratio of VLO to VHI will be appropriate for the ratio of K and J so the summation of the power PWM stage and the
finesse PWM stage will provide the full range of N bits. This summation is accomplished with a
low pass filter and time-division
multiplexing of the two PWM stages. A micro controller (MCU) is used to apply a sample packet distribution
algorithm to provide more resolution by reducing quantization
noise in the audio band of interest. The MCU is also used to calibrate the VLO or VHI, or to calibrate the PWM timing of the two PWM stages to achieve appropriate performance.