244results about How to "Reduce signal distortion" patented technology

An apparatus for transmitting data in a communication system using a Low Density Parity Check (LDPC) matrix is provided. The apparatus includes an interleaver for interleaving a descending bit-ordered codeword having a predetermined size and in accordance with a predetermined modulation scheme; and a bit mapper for mapping codeword bits constituting the interleaved codeword in accordance with a predetermined mapping scheme that takes into account degrees of the codeword bits and reliability characteristics of modulation symbol-constituting bits based on the predetermined modulation scheme.

A direct access arrangement (DAA) device is provided that is configured to interface a security alarm modem with a phone network. The DAA device comprises a receive optical isolator (OI) module having a receive input side and a receive output side. The receive input side includes a receive input line configured to receive a remote signal from the phone network. The receive output side includes a receive output line configured to convey the remote signal to a security alarm modem. First and second transmit OI modules are provided that each have a transmit input side and a transmit output side. The transmit input sides have transmit input lines joined in parallel with one another and configured to receive transmit signals from the security alarm modem. The transmit output sides have transmit output lines joined in parallel with one another and configured to convey the transmit signals to the phone network. An impedance matching module is joined to the transmit output sides of the first and second transmit OI modules and configured to provide impedance matching with the phone network. Optionally, the transmit output lines from the first and second transmit OI modules may be joined in parallel with the receive input line. The first and second transmit OI modules may include first and second LEDs, respectively, that draw substantially equal diode currents. The receive and first and second transmit OI modules may each have an associated diode current, where the receive module is interconnected with the first and second transmit OI modules such that the diode current collectively utilized by the first and second transmit OI modules changes by an amount that is substantially equal in amplitude, but opposite in polarity, to the diode current utilized by the receive OI module.

An optical transmitter for generating a modulated optical signal for transmission over dispersive fiber optic links in which a broadband analog radio frequency signal input is applied to a modulation circuit for directly modulating a semiconductor laser with the analog signal input. The transmitter may further include a temperature sensor in proximity to the laser and a negative feedback control circuit coupled to the temperature sensor for adjusting the temperature of the laser in response to an output characteristic of the laser, such as linearity.

A method for transmitting data in a communication system using a Low Density Parity Check (LDPC) matrix includes generating an LDPC codeword by encoding information data bits, interleaving the LDPC codeword, mapping the interleaved LDPC codeword to a modulation signal, and generating a mapped signal by mapping the LDPC codeword bits separately to a bit corresponding to a real part and a bit corresponding to an imaginary part of said modulation signal, among bits constituting the modulation signal, generating a modulation signal by high-order-modulating the mapped signal and Radio Frequency (RF)-processing the modulation signal, and transmitting the RF-processed signal via a transmission antenna.

Provided is a method for transmitting data in a communication or broadcasting system using a linear block code by generating a codeword by encoding input information data bits, interleaving the codeword; outputting modulation signal-constituting bits by bit-mapping the interleaved codeword using a bit-mapping table predetermined depending on a modulation scheme and a coding rate, outputting a modulation signal by modulating the modulation signal-constituting bits and transmitting the modulation signal via a transmit antenna.

Provided is a semiconductor memory module capable of decreasing a parasitic capacitance and a parasitic inductance which are incidental to a signal transmission path, thereby reducing a distortion of a signal waveform. In a memory module, four DRAMs are provided on a muttilayer printed circuit board in one line corresponding to a direction of arrangement of external terminals thereof and board terminal groups of the module are provided to make a pair along two long sides of the multilayer printed circuit board. The DRAM has external terminals extended from one of the long sides and external terminals extended from the other long side. Board terminals and board terminals in the board terminal group of the module are connected to the DRAM, and board terminals and board terminals in the board terminal group TGB of the module are connected to the DRAM.

A method of matching input amplitudes in a system wherein one or more of a plurality of inputs may be selected, with each input capable of having different characteristics, involving selecting an input signal and mapping the input signal to a predetermined signal amplitude through the use of level matching logic. The level matching logic may include a gain cell for increasing or decreasing the amplitude of the input signal.

A driver circuit includes a circuit 200, a transistor 101—1, and a transistor 101—2. A signal is selectively input from the circuit 200 to a gate of the transistor 101—1 and the transistor 101—2, so that the transistor 1011 and the transistor 101—2 are controlled to be on or off. The transistor 101—1 and the transistor 101—2 are turned on or off; thus, the wiring 112 and the wiring 111 become conducting or non-conducting.

In a bi-directional shift register and a liquid crystal display device having the bi-directional shift register, the shift register further includes a dummy stage for resetting a last stage. The dummy stage is reset by a control signal of the last stage or by the output signal of the dummy stage. Therefore, power consumption and layout area may be reduced. The shift register includes a plurality of stages and two dummy stages, and two selection signals for selecting shift direction is applied to each of the stages.

The invention relates to a method of reducing Peak-to-Average. Power Ratio in a transmitting device of a filter-hank multi-carrier system, which includes the steps of: performing constellation modulation (210) on data to be transmitted; performing K-point Discrete Fourier Transform (220) on a vector composed of K constellation symbols resulting from the constellation modulation: and performing Offset-Quadrature Amplitude Modulation (230) on a data vector resulting from the Discrete Fourier Transform, wherein the parameter K represents the number of subcarriers allocated for transmission of the data to be transmitted. With the solution proposed by the invention. PAPR of a signal can be significantly reduced without adding a large number of operations to thereby improve the efficiency of a power amplification circuit, to improve effective transmission, power and to alleviate nonlinear distortion of the signal during a power amplification.

The present invention, which aims at providing a semiconductor switch capable of reducing harmonic distortion, is made up of: an input terminal 101; an output terminal 102; a through FET 106 that is connected serially to the signal path between the input terminal 101 and the output terminal 102; a shunt FET 107 that is connected in between the output terminal 102 and the ground; and a distortion reducing circuit 120 that is connected in parallel with the through FET 106. In this semiconductor switch, the distortion reducing circuit 120 includes: a first diode 109 and a second diode 110 that are placed in parallel with each other; a first constant voltage source 111 and a second constant voltage source 112 that are placed in parallel with each other; and a FET 108.

A bass enhancing apparatus and method for enhancing bass include generating harmonics of the bass when an input signal is reproduced using a miniaturized speaker. The bass enhancing method includes extracting a bass component of an input signal, generating harmonics of the extracted bass component, synthesizing the generated harmonic signals and the input signal, and outputting the synthesizing result to an output terminal. The generating of the harmonics includes compressing a dynamic range of an amplitude level of each harmonic component at a predetermined distribution ratio.

An electronic circuit combines two or more individual wideband RF receivers or transceiver band circuits to produce a usable instantaneous bandwidth that is wider than the bandwidth of the individual band circuits. The electronic circuit overcomes the difficulties of combining bands to provide low signal distortion across the band edges and throughout the combined instantaneous bandwidth of the two or more individual band circuits. This electronic circuit utilizes an amplitude, time delay, and phase adjustment procedure that uses associated adjustable circuitry to eliminate misalignments between the two or more individual band circuits.

A technique for performing adaptive predistortion in a transmitter includes receiving, at a first input of an error signal unit, a delayed version of a baseband input signal. The technique also includes receiving, at a second input of the error signal unit, a power amplifier feedback signal from an output of a power amplifier. An input error signal that corresponds to a difference between the delayed version of the baseband input signal and the power amplifier feedback signal is then provided at an output of the error signal unit. The input error signal is then received at an input of a signal conditioner. An adjusted error signal that has a lower direct current offset than the input error signal is provided at an output of the signal conditioner.

A method and apparatus reduces error in a communication system that includes multiple orthogonal subcarriers by suppressing a subcarrier in a transmitting communication device and by equalizing a received signal in a receiving communication device. Subcarrier suppression is based on a determination of a signal quality metric with respect to each subcarrier or is based on a determination of excessive signal power overdriving an amplifier of the receiving communication device. Equalization of the received signal is based on an equalization function that reduces a multipath delay introduced to the transmitted signal when the multipath delay exceeds a tolerable multipath delay.

An optical transmitter for generating a modulated optical signal for transmission over a fiber optic link to a remote receiver including a laser; a modulator for directly amplitude modulating the laser with an analog RF signal to produce an optical signal including an amplitude modulated information-containing component; and a phase modulated component and a phase modulator coupled to the output of the laser for reducing the distortion present in the received optical signal at the remote receiver.

It is an object to suppress deterioration in characteristics of a transistor in a driver cricuit. A driver circuit includes a first transistor, a second transistor including a gate and one of a source and a drain to which a second signal is inputted, a third transistor whose gate is electrically connected to one of a source and a drain of the first transistor and which controls whether a voltage state of an output signal is set or not by being turned on / off, and a fourth transistor whose gate is electrically connected to the other of the source and the drain of the second transistor and which controls whether a voltage state of an output signal is set or not by being turned on / off.

Provided is a distributed Doherty power amplifier exhibiting high efficiency and linearity at a wide range of bandwidths, the distributed Doherty power amplifier including a first amplifier; a second amplifier, which is connected to the first amplifier in parallel; a first shifting unit, which is interconnected between the input of the first amplifier and the input of the second amplifier and inverses the phase of the input of the second amplifier; and a second shifting unit, which is interconnected between the output of the first amplifier and the output of the second amplifier and inverses the phase of the output of the second amplifier, wherein the first amplifier and the second amplifier are Doherty power amplifiers, and each of the Doherty power amplifiers includes a carrier amplifier and a peaking amplifier, which are connected in parallel.

The invention discloses a homing signal space-time anti-interference digital signal processor which mainly solves the problem that the properties of original homing signals cannot be better reserved during interference resistance of the prior art. A processing process of the digital signal processor comprises the following steps of: (1) receiving homing signals by a receiving antenna with a rectangular structure; (2) sampling the homing signals by a digital collecting unit and sending digital samples to a digital orthogonal interpolation module to carry out orthogonal interpolation conversion; (3) converting space domain data into space-time data and dividing the space-time data into two paths, wherein one path is sent into a self-adaptive weight number calculation module, while the other path is sent into a self-adaptive anti-interference module; (4) in the self-adaptive weight number calculation module, calculating a self-adaptive weight number according to a linearly constrained minimum variance; and (5) transmitting the weight number into the self-adaptive anti-interference module to multiply by the other space-time data to finish homing signal interference suppression. The digital signal processor has small signal distortion and high decoding rate and can be applied to anti-interference processing of received homing signals.

A sampling switch is the one for sampling an input voltage and providing an output voltage, comprising a MOS transistor for being supplied by the input voltage to the source terminal thereof and providing the output voltage from the drain terminal thereof; and a gate voltage control unit for supplying a voltage to the gate terminal of the MOS transistor with a delayed time from the input voltage. This enables a change in the on-resistance of a MOS transistor used for a sampling switch to be suppressed to a minimum, thereby reducing a distortion of signals induced by a change in the on-resistance.

Embodiments of a circuit for use with an inter-chip connection that has a variable complex impedance (which can be conductive, capacitive or both), a system that includes the circuit, and a communication technique are described. This inter-chip connection may be formed between a microspring or an anisotropic film and a metal connector on or proximate to a surface of a chip. Moreover, the circuit may mitigate signal distortion associated with the variable complex impedance. For example, the circuit may include an internal impedance that is electrically coupled in series with the metal connector, and that has an impedance which dominates the variable complex impedance over a range of operating frequencies. Separately or additionally, the circuit may be adapted to correct for the signal distortion.

A sampling switch is the one for sampling an input voltage and providing an output voltage, comprising a MOS transistor for being supplied by the input voltage to the source terminal thereof and providing the output voltage from the drain terminal thereof; and a gate voltage control unit for supplying a voltage to the gate terminal of the MOS transistor with a delayed time from the input voltage. This enables a change in the on-resistance of a MOS transistor used for a sampling switch to be suppressed to a minimum, thereby reducing a distortion of signals induced by a change in the on-resistance.

An apparatus for transmitting data in a communication system using a Low Density Parity Check (LDPC) matrix is provided. The apparatus includes an interleaver for interleaving a descending bit-ordered codeword having a predetermined size and in accordance with a predetermined modulation scheme; and a bit mapper for mapping codeword bits constituting the interleaved codeword in accordance with a predetermined mapping scheme that takes into account degrees of the codeword bits and reliability characteristics of modulation symbol-constituting bits based on the predetermined modulation scheme.

The invention belongs to an RF wireless receiver integration circuit technical field, in particular to an orthogonal down-frequency mixer with low power loss and high performance. The invention consists of an RF conversion transformer, an LO switch class, an IF load class and a power supply bias; wherein, the RF conversion transformer amplifies and transmits the received RF current signals; the orthogonal LO switch class leads the RF current signals to be alternatively output on an output differential load by a LO frequency with the phase difference of 90 DEG, thus implementing that the RF frequency multiplied by the orthogonal LO frequency obtains the orthogonal IF signal which is then output on the load. Compared with traditional Kilbert frequency mixers, the circuit structure replaces the differential transistor of RF amplification class by an on-chip integration amplifier, which can lead the frequency mixer to be applicable to low power voltage and dramatically reduce circuit noise and signal distortion; two orthogonal LO switch classes are combined into one circuit, which leads the frequency mixer to output orthogonal IF signals, simplifies the design of the wireless receiver and obviously reduces the power loss of the frequency mixer module.

An optical receiver having an electronic dispersion-compensation module with two parallel signal-processing branches configured to provide a greater range of dispersion compensation than that provided by a prior-art device of comparable implementation complexity. In an example embodiment, each of the signal-processing branches includes a respective bank of finite-impulse-response filters that are configured in accordance with a different respective approximation of the group delay that needs to be compensated. The two group-delay approximations used by the filter banks rely on different respective step functions, each having a respective plurality of quantized steps, with the transitions between adjacent steps in one step function being spectrally aligned with the flat portions of the corresponding steps in the other step function. The filter banks may be further configured to apply different respective frequency-dependent phase-shift and / or amplitude-scaling profiles designed to reduce signal distortions associated with the transitions between adjacent steps in the step functions.