758 results about "Low-density parity-check code" patented technology

Low density parity check (LDPC) codes (LDPCCs) have an identical code blocklength and different code rates. At least one of the rows of a higher-rate LDPC matrix is obtained by combining a plurality of rows of a lower-rate LDPC matrix with the identical code blocklength as the higher-rate LDPC matrix.

An interleaving method performed by a transmitter for a communication system with quasi-cyclic low-density parity-check codes, spatial multiplexing, and T transmit antennas is used for applying permutation to N cyclic blocks of a codeword in order to map bits of the permutated cyclic blocks onto T constellation words constituting multiple spatial-multiplexing blocks from the codeword. Each cyclic block consists of Q bits.

An apparatus for transmitting data in a communication system using a Low Density Parity Check (LDPC) matrix is provided. The apparatus includes an interleaver for interleaving a descending bit-ordered codeword having a predetermined size and in accordance with a predetermined modulation scheme; and a bit mapper for mapping codeword bits constituting the interleaved codeword in accordance with a predetermined mapping scheme that takes into account degrees of the codeword bits and reliability characteristics of modulation symbol-constituting bits based on the predetermined modulation scheme.

Data stored in non-volatile storage is decoded using iterative probabilistic decoding. An error correcting code such as a low density parity check code may be used. In one approach, initial reliability metrics, such as logarithmic likelihood ratios, are used in decoding sensed states of a set of non-volatile storage element. The decoding attempts to converge by adjusting the reliability metrics for bits in code words which represent the sensed state. Soft data bits are read from the memory if the decoding fails to converge. Initial reliability metric values are provided after receiving the hard read results and at each phase of the soft bit operation(s). In one embodiment, a second soft bit is read from the memory using multiple subsets of soft bit compare levels. While reading at the second subset of compare levels, decoding can be performed based on the first subset data.

Embodiments of decoders having early decoding termination detection are disclosed. The decoders can provide for flexible and scalable decoding and early termination detection, particularly when quasi-cyclic low-density parity-check code (QC-LDPC) decoding is used. In one embodiment, a controller iteratively decodes a data unit using a coding matrix comprising a plurality of layers. The controller terminates decoding the data unit in response to determining that the decoded data units from more than one layer decoding operation satisfy a parity check equation and that the decoded data units from more than one layer decoding operation are the same. Advantageously, the termination of decoding of the data unit can reduce a number of iterations performed to decode the data unit.

A communications transceiver for transmitting and receiving coded communications, with the coding corresponding to a low-density parity check code, is disclosed. A set of available code word lengths and code rates are to be supported by the transceiver. These available code word lengths and code rates are implemented as a subset of starting code word lengths, which are length-reduced by shortening and puncturing selected bit positions in the starting code word length to attain the desired one of the available code word lengths and code rates. The bit positions to be shortened and punctured are selected in a manner that avoids interference between the shortened and punctured bit positions, and that attains excellent code performance.

Data stored in non-volatile storage is decoded using iterative probabilistic decoding and multiple read operations to achieve greater reliability. An error correcting code such as a low density parity check code may be used. In one approach, initial reliability metrics, such as logarithmic likelihood ratios, are used in decoding read data of a set of non-volatile storage element. The decoding attempts to converge by adjusting the reliability metrics for bits in code words which represent the sensed state. If convergence does not occur, e.g., within a set time period, the state of the non-volatile storage element is sensed again, current values of the reliability metrics in the decoder are adjusted, and the decoding again attempts to converge. In another approach, the initial reliability metrics are based on multiple reads. Tables which store the reliability metrics and adjustments based on the sensed states can be prepared before decoding occurs.

Data stored in non-volatile storage is decoded using iterative probabilistic decoding and multiple read operations to achieve greater reliability. An error correcting code such as a low density parity check code may be used. In one approach, initial reliability metrics, such as logarithmic likelihood ratios, are used in decoding read data of a set of non-volatile storage element. The decoding attempts to converge by adjusting the reliability metrics for bits in code words which represent the sensed state. If convergence does not occur, e.g., within a set time period, the state of the non-volatile storage element is sensed again, current values of the reliability metrics in the decoder are adjusted, and the decoding again attempts to converge. In another approach, the initial reliability metrics are based on multiple reads. Tables which store the reliability metrics and adjustments based on the sensed states can be prepared before decoding occurs.

A parallel concatenated low density parity check (LDPC) code having a variable code rate is provided by generating, upon receiving information bits, a first component LDPC code according to the information bits, interleaving the information bits according to a predetermined interleaving rule, and generating a second component LDPC code according to the interleaved information bits. With use of the parallel concatenated LDPC code, a mobile communication system can use a Hybrid Automatic Retransmission Request (HARQ) scheme and an Adaptive Modulation and Coding (AMC) scheme without restriction.

Provided are a transmitting apparatus, a receiving apparatus and methods of puncturing and depuncturing of parity bits. The transmitting apparatus includes: a zero padder configured to pad at least one zero bit to input bits; an encoder configured to generate a Low Density Parity Check (LDPC) codeword by performing LDPC encoding with respect to the bits to which the at least one zero bit is padded; a parity interleaver configured to interleave LDPC parity bits constituting the LDPC codeword; and a puncturer configured to puncture at least a part of the interleaved LDPC parity bits based on a pre-set puncturing pattern.

An apparatus and a method for receiving a signal in a communication system using a Low Density Parity Check (LDPC) code. The apparatus and the method includes decoding a received signal according to a hybrid decoding scheme, wherein the hybrid decoding scheme is generated by combining two of a first decoding scheme, a second decoding scheme, and a third decoding scheme.

An apparatus and method are provided for transmitting a signal in a communication system using a low density parity check (LDPC) code. An LDPC codeword is generated by encoding an information word at a coding rate. A puncturing pattern is generated when a hybrid automatic repeat request (HARQ) scheme to be applied to the LDPC codeword is an incremental redundancy (IR) scheme. An additional pattern is generated when the HARQ scheme to be applied to the LDPC codeword is a partial chase combining (CC) scheme. A signal is transmitted by applying the puncturing pattern to the LDPC codeword at an associated coding rate when the HARQ scheme to be used is the IR scheme. A signal is transmitted by applying the additional pattern to the LDPC codeword at an associated coding rate when the HARQ scheme to be used is the partial CC scheme.

Low density parity check (LDPC) codes (LDPCCs) have an identical code blocklength and different code rates. At least one of the rows of a higher-rate LDPC matrix is obtained by combining a plurality of rows of a lower-rate LDPC matrix with the identical code blocklength as the higher-rate LDPC matrix.

Modem coding and modulation techniques have greatly improved the transmission and reception of signals. A method is described including receiving a signal de-mapping the signal into a first and second substream, decoding the first and second substream using a low density parity check decoding process, and combining the first and second decoded substream into a single data stream. An apparatus is described including a symbol de-mapper that receives a signal de-maps the modulation symbols in the signal into a first and second substream, a first decoder that decodes the first substream using a low density parity check coding process at a first decoding rate, a second decoder that decodes the second substream at a second encoding rate, and a combiner that combines the first substream and the second substream into a single data stream.

The invention embodiment provides a coded modulation method for low density parity check code, a low density parity check code coded processing can be performed for an information sequence to obtain a code word, and the interweave processing can be performed for the code word, then the modulated processing can be performed for the code word by interweave processing; meanwhile, the invention embodiment also provides a coded modulation apparatus for the low density parity check code. The technical scheme disclosed by the invention embodiment is based on the importance of low density parity check code degree distribution, and the different bits on a star map in high order modulation have different reliabilities, and the excellent coded modulation gain can be obtained.

A method for transmitting data in a communication system using a Low Density Parity Check (LDPC) matrix includes generating an LDPC codeword by encoding information data bits, interleaving the LDPC codeword, mapping the interleaved LDPC codeword to a modulation signal, and generating a mapped signal by mapping the LDPC codeword bits separately to a bit corresponding to a real part and a bit corresponding to an imaginary part of said modulation signal, among bits constituting the modulation signal, generating a modulation signal by high-order-modulating the mapped signal and Radio Frequency (RF)-processing the modulation signal, and transmitting the RF-processed signal via a transmission antenna.

The invention discloses a speed matching method of the limited-length circular cache of a low-density parity-check code. The method includes the following steps of conducting a structured low-density parity-check code encoding on the data bit of an inputted information block, and determining the size of the one-dimensional limited-length circular cache according to the encoding result; selecting a redundant version value from a plurality of preset redundant version values according to the retransmission times of the mixed retransmission request, and determining the initial position of the data bit of the formed mixed retransmission request data packet read from the one-dimensional limited-length circular cache according to the selected redundant version value; and reading the mixed automatic retransmission request data packet composed of specific-length data from the initial position in order, and sending the mixed automatic retransmission request data packet out. The respective corresponding initial positions of the multiple preset redundant version values are evenly or almost evenly distributed on the one-dimensional limited-length circular cache.

A multiple access scheme is described. One or more encoders are configured to encode a plurality of bit streams using Low Density Parity Check (LDPC) coding. The bit streams correspond to a respective plurality of terminals. The plurality of bit streams are converted to provide a multiple access scheme for the terminals.

Data stored in non-volatile storage is decoded using iterative probabilistic decoding. An error correcting code such as a low density parity check code may be used. In one approach, initial reliability metrics, such as logarithmic likelihood ratios, are used in decoding sensed states of a set of non-volatile storage element. The decoding attempts to converge by adjusting the reliability metrics for bits in code words which represent the sensed state. Soft data bits are read from the memory if the decoding fails to converge. Initial reliability metric values are provided after receiving the hard read results and at each phase of the soft bit operation(s). In one embodiment, a second soft bit is read from the memory using multiple subsets of soft bit compare levels. While reading at the second subset of compare levels, decoding can be performed based on the first subset data.

A transmitting apparatus and a receiving apparatus are provided. The transmitting apparatus includes: an encoder configured to generate a low density parity check (LDPC) codeword by performing LDPC encoding; an interleaver configured to interleave the LDPC codeword; and a modulator configured to modulate the interleaved LDPC codeword according to a modulation method to generate a modulation symbol. The interleaver includes a block interleaver formed of a plurality of columns each comprising a plurality of rows, and the block interleaver is configured to divide the plurality of columns into at least two parts and interleave the LDPC codeword.

Methods and systems of low density parity check coded (LDPCC) coding are disclosed herein in which a set of LDPC codes ensure reliable transmission for channels in which modulation symbols may undergo attenuation in a random fashion. Methods and systems of LDPC coding disclosed herein include choosing a code blocklength and concatenating codewords into which a data packet can be encoded. To optimize the coding scheme, first, codeword shortening is performed to ensure an integer number of codewords for a desired packet length. The codewords may then be punctured or repeated to ensure an integer number of channel symbols per codeword. Shortening and puncturing repetition methods are implemented to yield minimum overhead while keeping the effective coding rate low.

A transmitting apparatus and a receiving apparatus are provided. The transmitting apparatus includes an encoder configured to generate a low density parity check (LDPC) codeword by performing LDPC encoding, an interleaver configured to interleave the LDPC codeword, and a modulator configured to modulate the interleaved LDPC codeword according to a modulation method to generate a modulation symbol. The interleaver performs interleaving by dividing the LDPC codeword into a plurality of groups, rearranging an order of the plurality of groups in group units, and dividing the plurality of rearranged groups based on a modulation order according to the modulation method.

A digital communication decoding method for low-density parity-check coded messages. The decoding method decodes the low-density parity-check coded messages within a bipartite graph having check nodes and variable nodes. Messages from check nodes are partially hard limited, so that every message which would otherwise have a magnitude at or above a certain level is re-assigned to a maximum magnitude.

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 4 / 15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256-symbol mapping.

The present invention discloses a method for channel coding and modulation mapping in HARQ of the LDPC code, comprising: performing structural LDPC encoding of an information bit sequence with a length of K input by a channel encoder, and sending a generated codeword to a HARQ buffer; rearranging codeword bits of a LDPC HARQ mother code in the HARQ buffer, and sequentially selecting codeword bits to generate a binary sequence of a HARQ packet; mapping codeword bits of the HARQ packet to a constellation, and high-order bits in encoding blocks of the HARQ packet being mapped to high reliability bits in the constellation. The present invention provides the LDPC codeword with the maximal constellation gain, so that the LDPC HARQ channel encoding has the optimal performance.

A channel interleaving method and apparatus in a communication system using a low density parity check (LDPC) code. Upon receipt of information data bits, an encoder encodes the information data bits into an LDPC codeword using a predetermined coding scheme. A channel interleaver interleaves the LDPC codeword according to a predetermined channel interleaving rule. A modulator modulates the channel-interleaved LDPC codeword into a modulation symbol using a predetermined modulation scheme.

Quasi-cyclic LDPC (Low Density Parity Check) code construction is presented that ensures no four cycles therein (e.g., in the bipartite graphs corresponding to the LDPC codes). Each LDPC code has a corresponding LDPC matrix that is composed of square sub-matrices, and based on the size of the sub-matrices of a particular LDPC matrix, then sub-matrix-based cyclic shifting is performed as not only a function of sub-matrix size, but also the row and column indices, to generate CSI (Cyclic Shifted Identity) sub-matrices. When the sub-matrix size is prime (e.g., each sub-matrix being size q×q, where q is a prime number), then it is guaranteed that no four cycles will exist in the resulting bipartite graph corresponding to the LDPC code of that LDPC matrix. When q is a non-prime number, an avoidance set can be used and / or one or more sub-matrices can be made to be an all zero-valued sub-matrix.

Transmitter apparatus to broadcast coded orthogonal frequency-division multiplexed (COFDM) radio-frequency carriers conveying digital television (DTV) signals encoded using Bose-Chaudhuri-Hocquenghem (BCH) coding concatenated with subsequent low-density parity-check coding (LPDC) transmits the same coded DTV signals twice some time apart. The coded DTV signals are mapped to quadrature amplitude modulation (QAM) of the COFDM carriers. Preferably, the circular Fourier transforms of COFDM symbols in the earlier transmissions are rotated one half revolution respective to the circular Fourier transforms of corresponding COFDM symbols in the later transmissions. Receiver apparatus combines the earlier and later transmissions of twice-transmitted COFDM signals as part of iterative procedures for de-mapping QAM and decoding the concatenated BCH-LDPC coding of the DTV signals.

The invention provides a method and device for encoding a low-density parity check code. The method comprises the following steps of: comparing a mother code rate and a transmission code rate which are supported by a uniform basic matrix; determining the length K'of an input information grouping bit according to a comparison result; determining an encoding matrix of the low-density parity check (LDPC) code according to the uniform basic matrix and an expansion factor; determining an information bit to be encoded according to the received information grouping bit with the length of K'; and performing LDPC encoding on the information bit to be encoded by using the encoding matrix, and processing a mother code word bit obtained through encoding to acquire a code word bit to be transmitted. By the method and device for encoding the LDPC code, the basic matrix and the expansion factor are determined; the input information grouping length is determined or the encoding matrix is processed according to the received transmission code rate, so the code word which is in accordance with the transmission code rate can be acquired; on the basis of the optimal performance, the changeability of the code rate is realized; furthermore, the hardware design complexity is reduced and the cost is lower.