638results about "Marginal circuit testing" patented technology

System and method for detecting transistor failure in large-scale integrated circuits by measuring IDDQ. A preferred embodiment comprises a switch structure for an integrated circuit made up of a plurality of main switches (such as main switch 410) selectively coupling a power sub-domain to a power source pin, a plurality of pi-switches (such as pi-switch 415) selectively coupling pairs of power sub-domains, and a plurality of IDDQ switches (such as IDDQ switch 425) selectively coupling the power sub-domains to a VIDDQ pin. The pi-switches can decouple the power sub-domains while the IDDQ switches can enable the measurement of the quiescent current in the power sub-domains. The use of pi-switches and IDDQ switches can permit the measurement of the quiescent current in the power sub-domains without requiring the use of isolation buffers and needed to powering on and off the integrated circuit between current measurements in the different power sub-domains.

A system and method for compensating an amplifier apparatus for low frequency and / or DC components of an externally applied input signal as well as for any voltage offsets contributed by the amplifier circuitry. Band-limited servo feedback is applied to predetermined nodes in the forward gain path to null out unwanted signal components, leaving a residual signal that, when amplified, will be centered around ground, so that the full dynamic range of the amplifier system may be utilized. Consequently, the signal-to-noise ratio available at the output of the amplifier system will be maximized. The servo compensation may either operate in continuous time, or it may be held constant once a suitable level of compensation has been established, or it may be adjusted from time to time to accommodate slow variations of the average DC component of the input signal.

Voltage-binning of individual integrated circuits is achieved by operating those integrated circuits at a plurality of required clock frequencies and for each of those frequencies determining the minimum supply voltage level which produces a pass result for a series of applied test vectors.

A semiconductor leakage current detector of the present invention includes a first analog switch which causes a current to be measured to flow or to be cut off, a second analog switch which causes a reference current to flow or to be cut off, an integral capacitance element which is connected by the first analog switch and the second analog switch and is charged with the current to be measured or the reference current, a discharge unit which discharges the integral capacitor, and a comparison unit which compares the reference voltage with each of an integral voltage generated in the integral capacitor by a reference current after the discharge of the integral capacitor and an integral voltage generated in the integral capacitance element by the current to be measured after the discharge of the integral capacitor.

A method and system for detecting and locating defects in an integrated circuit. A time-varying input signal is applied to the integrated circuit, power signals produced at a plurality of respective ordered connections in response to the input signal are measured, and one or more defects in the integrated circuit are identified from the power signals so measured. A system is provided having a probe for connecting to the die of an integrated circuit prior to final packaging, a testing system for applying transient input signals to the die and acquiring die power signal measurements in response thereto, and a data processor for determining whether the power signal measurements indicate the presence of a defect in the die. Also provided is a method for reducing the effect of contact resistance from test probe connections. As a way of implementing the approach of the method and system there is also provided an integrated circuit having a plurality of ordered connections to the power grid and a plurality of calibration circuits associated with respective ordered connections so as to selectively inject transient signals onto the power grid at respective locations.

Systems, methods and program codes are provided for testing multi-core processor chip structures. Individual processor core power supply voltages are provided through controlling individual power supplies for each core, in one aspect to ensure that one or more cores operate at clock rates in compliance with one or more performance specifications. In one example, a first power supply voltage supplied to a first processing core differs from a second core power supply voltage supplied to a second processing core, both cores operating in compliance with a reference clock rate specification. Core power supply voltages may be selected from ordered discrete supply voltages derived by progressively raising or lowering a first supply voltage, optionally wherein the selected supply voltage also enables the core to operate within another performance specification.

A method for generating stimuli and test responses for testing faults in a scan-based integrated circuit in a selected scan-test mode or a selected self-test mode, the scan-based integrated circuit containing a plurality of scan chains, N clock domains, and C cross-clock domain blocks, each scan chain comprising multiple scan cells coupled in series, each clock domain having one capture clock, each cross-clock domain block comprising a combinational logic network. The method comprises compiling the scan-based integrated circuit into a sequential circuit model; specifying input constraints on the scan-based integrated circuit during a shift and capture operation; specifying a clock grouping to map the N clock domains into G clock domain groups, where N>G>1; transforming the sequential circuit model into an equivalent combinational circuit model according to the input constraints and the clock grouping; and generating the stimuli and test responses on the equivalent combinational circuit model according to the input constraints.

A test system for an integrated circuit includes a grouping module grouping measurement points on basis of values of the quiescent supply current and setting measurement point groups; an average value setting module setting a weighted average value minimizes the sum of dispersion of the quiescent supply current; a calculating module calculating a maximum estimated value of dispersion of the quiescent supply current on the basis of the weighted average value; and a judgment module judging whether the integrated circuit passes or fails the judgment specification.

The objective of this invention is to provide a type of semiconductor integrated circuit which can lessen solution in the circuit area to the minimum necessary level, and can lessen the leakage current in the standby state so as to cut the power consumption, and which allows Iddq test to determine whether it is passed or defective. Logic circuit 10 composed of low threshold voltage transistors and switching circuit 20 composed of transistors having the standard threshold voltage are set. In the operation, the switching circuit is turned ON, and a driving current is fed to logic circuit 10. On the other hand, in the standby mode, the switching circuit is turned OFF, and the path of the leakage current is cut off to lessen generation of the leakage current. In the case of Iddq test, different bulk bias voltages are applied to the channel regions of PMOS transistors and NMOS transistors from an IC tester through pads P1 and P2. In this way, the leakage current can be lessened on a low level, and whether the semiconductor integrated circuit is passed or defective can be judged from the results of the current measurement.