860 results about "Production testing" patented technology

We introduce a new Periodic micro coaxial transmission line (PMTL) that is capable of sustaining a TEM propagation mode up to THz band. The PMTL can be manufactured using the current photolithographic processes. This transmission line can be embedded in microscopic layers that allow many new applications. We use the PMTL to develop a wideband highly scalable connector that is then used in a Probe that can be used for connecting to microscopic scale Integrated Circuits with picoseconds High Speed Digital and near THz Analogue performance in various stages of development from R&D to production testing. These probes, in one embodiment, provide a thin pen-like vertical probe tip that matches the die pad pattern precisely that can be as agile as a high speed plotter pen, connecting on the fly to any die pattern on a wafer. This approach allows the most valuable part of the test, namely the wafer to remain stationary and safe, and the least costly part of the test, namely the probe to take most of the wear and tear. We further use the embedded PMTL to develop a modular, scaleable and fully automated Universal Test Fixture for testing chips in various stages of development mainly for digital IC chips that can be utilized in production lines with pick and place of chips on tape to test every chip before insertion into circuits. One embodiment includes a low profile wideband Signal Launcher and an alligator type RF Clip that can be used at the edge of PCB's directly for validation broads. The Signal Launcher is used to develop a new versatile Flush Top Test Fixtures for individual device testing in various stages of development from die, to packaged, to Module, to Circuit Boards. The PMTL can also provide Confined Field Interconnects (CFI) between various elements on semiconductor wafers to reduce parasitic and radiation losses and practically eliminating cross talk, thus, increasing the speed of digital IC's. The PMTL is also used to develop a Universal Test Socket, and a Hand Probe with performance up to 220 GHz.

Compact exhaust mixer assemblies comprising a compact mixer and a trimmable open centerbody are provided. The trimmable center body allows for adjustments of the open centerbody after manufacturing and during production testing. The trimmable open centerbody may be used to compensate for production tolerances making it possible to obtain the desired core effective area for proper engine operation. The compact mixer may be either lobed or serrated. The compact exhaust mixer assemblies have a length of about half that of conventional exhaust mixer assemblies.

A novel and useful self-calibration based production line testing mechanism utilizing built-in closed loop measurements in the radio to calibrate the output power of an external power amplifier coupled to a SoC radio. The mechanism is applicable during production line testing and calibration which is performed on each SoC and associated external power amplifier after assembly at the target PCB of the final product. The mechanism calibrates the TX output power in three phases based on loopback EVM measurements. In a first phase, the PPA in the radio (SoC) is calibrated and gain versus output power is stored in a gain table in on-chip NVS. In a second phase, the maximum PPA TX power is determined using closed loop EVM measurements. The external PA is calibrated in a third phase and the maximum PA power is determined. During this third phase, the maximum power of the device is calculated, compared to the requirements of the particular standard and a pass / fail determination is thereby made.

Large, complex SoCs comprise interconnections of various functional blocks. Such functional blocks contain scan chains that are used for their individual production testing. The present invention utilizes these scan chains as a tool in the debugging of these SoCs by providing the internal contents of registers and memories contained on the SoC device. Accordingly, both hardware and software designers are provided a means to observe the effect of their designs on the internal operation of the SoC device. The invention is compatible with current integrated circuit design methodology and requires minimal area on the SoC for support circuitry.

A high volume testing / formatting process is provided for Universal Serial Bus-based (USB-based) electronic data flash cards (USB devices) that meets the increasing demand for USB electronic data flash cards (USB devices). A test host is simultaneously coupled to the multiple USB devices (e.g., using a multi-port card reader or a probe fixture), a controller endpoint value is read from each of the USB devices and verified with a known good value, and then testing / formatting is performed on each of the USB devices by writing predetermined data into each USB device in a pipelined manner, then reading out and testing the predetermined data. In one embodiment, the test host implements a special USB driver that blocks standard USB registration procedures upon detecting the plurality of USB devices. Control and / or boot code data are written onto the flash memory device (i.e., instead of being provided on a controller ROM).

The invention discloses a fault tolerance design method for a solid-state memory device, in which standby redundant memory particles are additionally added in design of a circuit board of a memory device, when the device has flash memory fault in production back-end test or usage, the failed particles are substituted by the redundant memory particles, thereby ensuring that excellent rate of production of the memory device cannot be influenced even encapsulation test is not performed on the particles; simultaneously, service life of the device is effectively prolonged by adding the redundant memory particles in the method, when the flash memory particles in the device reach certain service life, the flash memory particles are substituted by the redundant particles or idle particles, so that the service life of the device is effectively prolonged through the continuous substitution. The method can be implemented in process of device production test and / or usage.

Systems, processes, and structures allow enhanced near-field testing of the uplink and / or downlink performance of MIMO wireless devices (DUT), such as for any of product development, product verification, and / or production testing. Signal channels may preferably be emulated to test the performance of a device under test (DUT) over a range of simulated distances, within a near-field test environment. An enhanced process provides automated testing of a DUT over a wireless network, e.g. such as but not limited to a WLAN. The enhanced MIMO channel emulator may preferably be operated over a high dynamic range.

Large, complex SoCs comprise interconnections of various functional blocks. Such functional blocks contain scan chains that are used for their individual production testing. The present invention utilizes these scan chains as a tool in the debugging of these SoCs by providing the internal contents of registers and memories contained on the SoC device. Accordingly, both hardware and software designers are provided a means to observe the effect of their designs on the internal operation of the SoC device. The invention is compatible with current integrated circuit design methodology and requires minimal area on the SoC for support circuitry.

Systems, processes, and structures provide near-field transmit power measurement for MIMO wireless devices (DUT), such as for any of product development, product verification, and / or production testing. A test signal, such as comprising a pulse train signal, is provided to a MIMO device under test (DUT), wherein portions of the test signal controllably steered and sequentially transmitted from each of the device antennas, to one or more test antennas that are positioned in close proximity to the MIMO DUT. The near-field power of the received test signals is measured, to quickly and efficiently determine if one or more data streams of the MIMO DUT has a problem.