120results about How to "Improve test throughput" patented technology

A digital communications test system and method for testing a plurality of devices under test (DUTs) in which multiple sets of a single vector signal analyzer (VSA) and single vector signal generator (VSG) can be used together to perform error vector magnitude (EVM) measurements for one or more DUTs in parallel, including one or more of composite, switched and multiple input multiple output (MIMO) EVM measurements. This allows N pairs of a VSA and VSG to test N DUTs with N×N MIMO in substantially the sane time as a single VSA and VSG pair can test a single DUT, thereby allowing a substantial increase in testing throughput as compared to that possible with only a single VSA and VSG set.

The invention provides, in one embodiment, a device for performing scrub testing on a plurality of samples simultaneously, including a plurality of scrubbing devices. A stage is provided which positions the plurality of samples in contact with the plurality of scrubbing devices. The scrubbing devices can individually be provided with different weights to produce different forces on the samples. A motion producing device produces one or both of linear and rotational motion between the brushes and the samples. The scrubbing devices are held in the stage so as move freely vertically.

A digital communications test system and method for testing a plurality of devices under test (DUTs) in which multiple sets of a single vector signal analyzer (VSA) and single vector signal generator (VSG) can be used together to perform error vector magnitude (EVM) measurements for one or more DUTs in parallel, including one or more of composite, switched and multiple input multiple output (MIMO) EVM measurements. This allows N pairs of a VSA and VSG to test N DUTs with NxN MIMO in substantially the sane time as a single VSA and VSG pair can test a single DUT, thereby allowing a substantial increase in testing throughput as compared to that possible with only a single VSA and VSG set.

The invention discloses a chemiluminescence immunoassay system, as well as a method and an application thereof. The chemiluminescence immunoassay system comprises a fluid control unit as well as a three-dimensional motion sample feeding platform, a temperature control unit, a magnetic field control module and an optical detecting module, wherein the three-dimensional motion sample feeding platform, the temperature control unit, the magnetic field control module and the optical detecting module are connected with each other in sequence; and the fluid control unit is connected with the temperature control unit. The chemiluminescence immunoassay system disclosed by the invention has the advantages as follows: with a capillary tube as a reactor, reagent transportation and reaction are both carried out in a water-in-oil type liquid drop by using a capillary tube liquid drop technology, so that a stable reaction condition is kept, and crossed pollution between samples and reaction suppression caused by surface adsorption are effectively avoided. The chemiluminescence immunoassay system disclosed by the invention has the advantages of small size, high assay speed, high testing flux, automatic operation and flexibility in application and is suitable for analyzing single sample, batch samples and field rapid assay; medical demands of the masses can be preferably satisfied; meanwhile, the purchasing and operation cost of equipment is obviously reduced, and excellent social and economic benefits are obtained.

The invention discloses an IC feeler mechanism to do multiple paralleling particle placements simultaneously, which comprises the following parts: material supplying box, material-receiving box, input end IC transmitting mechanism, output end IC transmitting mechanism, testing part, transmitting tool and orbit transmitting mechanism, wherein the input end IC transmitting mechanism sucks the detected IC on the material supplying box to the transmitting tool to bear multiple particles of the detected IC; the transmitting tool utilizes orbit transmitting mechanism to transmit the transmitting tool into the testing part through orbit, which testes multiple particles of IC to move out the transmitting tool after testing; the output end IC transmitting mechanism classifies each tested IC in the transmitting tool to place in each receiving box. The invention reduces the exchanging, placing and depositing time of IC greatly, which improves the testing property effectively.

An Application Specific Distributed Test Engine (ASDTE) that provides an optimized set of test resources for a given application. The test engine resources, configuration, functionality, and even the number of test engines can be changed as different devices are tested, or as different test methodologies are used with the system. This can be done by including the test engine configuration as a part of the application files that are loaded during the system set-up. This approach differs from conventional testing systems which limit testing to a fixed, limited, or standard stimulus / response engine configuration intended to test a variety of devices. Some of the benefits of the Application Specific Distributed Test Engine Architecture include: (1) a very high test throughput, (2) the ability to adapt system functionality and capabilities to meet different and new, unforeseen device test requirements on a lot-by-lot basis on a production test floor, and (3) the ability to change the number of test engines to optimize tester channels and system utilization.

A system and method for testing and calibrating integrated sensor devices that improves the manufacturing test throughput of the devices. The system includes a tester, a temperature controller, and at least one probe station including a thermal chuck. The chuck can be heated to specified temperatures to achieve variable heating of a wafer, PCB, or pallet disposed thereon. The temperature controller adjusts the temperature of the chuck to a first specified level. The tester performs at least one first measurement of the output offset of each integrated sensor embodied as a die on the wafer, or as a device on the PCB or pallet. Next, the temperature controller adjusts the temperature of the chuck to a second specified level, and the tester performs at least one second measurement of the output offset of each integrated sensor at the second temperature level. The offset temperature coefficient (OTC) of each sensor is calculated based upon the output offset measurements performed at the first and second temperature levels, and optimal settings for calibrating the respective sensors are determined based upon the calculated OTC values. After the temperature of the chuck is brought back down to the first specified level, the tester programs the output offset calibration settings into each sensor.

The invention provides a detection device for reducing the test cost of semicondustor device. An test equipment includes a tester board that can be housed in a chamber, a plurality of sockets that are attached on a first main surface of the tester board and mounted respectively with semiconductor devices to be tested, a plurality of device testing units that are attached on a second main surface of the tester board and input predetermined test signals to the semiconductor devices as well as evaluate the semiconductor devices respectively based on the output signals output from the semiconductor devices according to the test signals, and a heat sink plate that cools off the device testing units, where a burn-in test and a characteristic test are carried out for the semiconductor devices while the semiconductor devices mounted on the sockets are heated, and the device testing units are cooled off by a dissipating unit in the chamber.