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43 results about "Time Stamp Counter" patented technology

The Time Stamp Counter (TSC) is a 64-bit register present on all x86 processors since the Pentium. It counts the number of cycles since reset. The instruction RDTSC returns the TSC in EDX:EAX. In x86-64 mode, RDTSC also clears the higher 32 bits of RAX and RDX. Its opcode is 0F 31. Pentium competitors such as the Cyrix 6x86 did not always have a TSC and may consider RDTSC an illegal instruction. Cyrix included a Time Stamp Counter in their MII.

Method and apparatus for complex time measurements

Apparatus used in an automatic test equipment, comprising a plurality of system modules. Each system module comprises a Time Measurement Unit. The Time Measurement Unit comprises a Global Time Stamping Module. The Global Time Stamping Module comprises a plurality of Global Time Stamping Cores that comprising: an information receiving section for receiving at least two information, an event receiving section for receiving at a Core Input events, an event determining section for determining events of interest from said received events appearing on said Core Input, and an instructing section for instructing a Time Stamp Memory to record a current status of a Time Stamp Counter corresponding to the Clock Information, if an event of interest is determined. The Global Time Stamping Module further comprises a supplying section for supplying said plurality of Global Time Stamping Cores with a common time base.
Owner:ADVANTEST CORP

Consistent distributed timestamp counters

When timestamp counters are distributed among multiple physical devices, variances in their timestamp values can occur, such as, but not limited to those cause by variances among clocks in these different devices, different routing delays, different components, etc. These differences may be same, but still not allow high enough precision, especially as packet and processing rates continue to increase (which also causes clocking rates of devices to increase). One implementation distributes a time advance signal to each of these devices, which each device independently uses to determine when to advance its timestamp counter in response to its clock signal. These timestamps may be generated according to IEEE 1588 Standard for a Precision Clock Synchronization Protocol for Networked Measurement and Control Systems; and / or Physical Layer Transceivers (PHYs) may be disposed in each of the different physical devices.
Owner:CISCO TECH INC

Global Synchronous Clock

Processor clock signals are generated for each processor in a HPC system, such that all the processor clock signals are of the same frequency. Furthermore, as part of a startup (boot) procedure, a process sets all time stamp counters (TSCs) of the processors, such they indicate identical times. Each blade of the HPC system recovers a recovered clock signal from a synchronous communication network, to which the blade is coupled. The blade generates a processor clock from the recovered clock signal and provides the processor clock to processor(s) on the blade. Each chassis is coupled to a second, system-wide, synchronous communication network, and each chassis synchronizes its chassis synchronous communication network with the system-wide synchronous communication system. Thus, all the processor clock signals are generated with the same frequency.
Owner:HEWLETT-PACKARD ENTERPRISE DEV LP

PTP clock synchronization system and clock synchronization method

PendingCN111181555AGuaranteed accuracyTroubleshoot valid clock signal inputPulse automatic controlSlave clockPHY
The invention discloses a PTP clock synchronization system. The system includes a master clock board and a slave clock board; a plurality of service single boards which are used for receiving a masterclock signal output by the master clock board and a slave clock signal output by the slave clock board; and a backboard which is used for forming signal connection leads among the master clock board,the slave clock board and the service single boards. Each service single board comprises a first clock selection unit used for determining one clock signal as a working clock signal according to thecurrent states of the master clock state signal and the slave clock state signal; and a digital phase-locked loop which is used for carrying out phase locking on the received working clock signal andthen generating an effective clock signal of a timestamp counter of the physical PHY chip. The invention also discloses a PTP clock synchronization method. According to the system and the method provided by the invention, a stable and effective clock signal can be provided for the timestamp counter of each service single board PHY chip in the clock board switching process.
Owner:RAISECOM TECH

SMV packet generator for digital energy meter communication protocol test

The invention provides an SMV packet generator for a digital energy meter communication protocol test. The SMV packet generator comprises a man-machine interactive system which comprises an industrial control machine which is externally connected to a first DDR2, a DOM, an input keyboard, an LCD and a first Ethernet module respectively, an embedded DSP system which comprises a BF609 module which is externally connected to a second DDR2, a FLASH and a second Ethernet module respectively, a time set module which comprises an antenna, a GPS receiver, a time stamp counter and a comparator which are connected in order, and a power supply module. The output end of the comparator is connected to the embedded DSP system. The time stamp counter is also externally connected to a pulse input module and a clock oscillator at the same time. Both the first Ethernet module and the second Ethernet module are provided with two paths of Ethernet interfaces. The man-machine interactive system, the embedded DSP system and a digital energy meter are in mutual communication and connection through the Ethernet. The SMV packet generator can be used in a digital energy meter communication protocol test, and the technical parameters of synchronization time delay, dispersion and sampling rate can be flexibly controlled.
Owner:ELECTRIC POWER RES INST OF GUANGDONG POWER GRID

Debug trace time stamp correlation between components

Debug time stamp counters in a computing device may be synchronized based on signals indicating awakening of a component of the computing device from a sleep state. A count from a global counter in a first component may be loaded into a replica global counter in a second component. The count from the global counter may be loaded into a first debug time stamp counter in the first component in response to a first preload signal indicating awakening of the first component from a sleep state or in response to a second preload signal indicating awakening of the second component from a sleep state. The count from the replica global counter may be loaded into a second debug time stamp counter in the second component in response to the second preload signal.
Owner:QUALCOMM INC

Time synchronous pluggable transceiver

The invention discloses a pluggable transceiver module (200) comprising a line receiver (208) connected to a unit interface transmitter (202), a line transmitter (206) connected to a unit interface receiver (204) and a timestamp counter (210) adapted to generate counter values based on clock signals received from an external source and to send the counter values to the line transmitter (206) and to the line receiver (208). The line transmitter (206) and the line receiver (208) are adapted to associate timing packets in a stream of data packets transmitted and received by the pluggable transceiver module (200) with counter values output by the timestamp counter (210).
Owner:TELEFON AB LM ERICSSON (PUBL)

Time correction method, device and system and storage medium

The invention relates to a time correction method, device and system and a storage medium, and the method comprises the steps: obtaining a first time synchronization message which carries a time synchronization timestamp and a preset code; recording a first timestamp corresponding to the moment when the preset code is detected, and deleting the preset code in the first time tick message to obtainan original time tick message; extracting a time synchronization timestamp in the original time synchronization message; and correcting the timestamp of the timestamp counter by using the time synchronization timestamp and the first timestamp, so that the timestamp of the timestamp counter and the timestamp of the timestamp counter sending the first time synchronization message have the same valueat the same moment. According to the method, the problem that the time information transmitted between the cross-service sub-frames is inaccurate in the prior art can be relieved, and the accuracy ofthe time information transmitted between the cross-service sub-frames is improved.
Owner:ZTE CORP

Method and device for measuring system manager interrupt time

The invention discloses a method and a device for measuring the system manager interrupt time. The method includes triggering SMI (system manager interrupt), and then reading the count of first TSC (time stamp counter) clocks in processors of SMM (system management modes); executing SMI processing programs corresponding to the SMI by the aid of main processors and then reading the count of second TSC clocks; judging whether the execution time corresponding to the SMI is longer than the maximum SMI time or not; updating the maximum SMI time, the SMI cumulative time and SMI trigger frequencies in OEMACPI (original equipment manufacturer advanced configuration and power interface) tables if the execution time corresponding to the SMI is longer than the maximum SMI time, and quitting the SMM. The count of the first TSC clocks is used as preset locations for storing first time stamps in memories. The count of the second TSC clocks is used as second time stamps. The method and the device have the advantages that the execution time of the SMI is acquired by the aid of the TSC clocks, accordingly, access delay can be shortened, the accuracy of the obtained execution time of the SMI can be improved, and parameters stored in the OEMACPI tables can be analyzed by operating systems and can be used for measuring the system performance.
Owner:SUZHOU LANGCHAO INTELLIGENT TECH CO LTD

Distributed Control Synchronized Ring Network Architecture

A ring network architecture includes multiple communication nodes configured in a ring. Wave pipelining is used to provide for high bandwidth and low latency on-chip communications. Each node implements a source-synchronized clocking scheme, such that there is no need to build an extensive low skew clock-tree across a large die area. A single reference clock signal is generated within a root node, and is routed through each of the nodes of the ring network in a unidirectional manner. Each node includes a timestamp counter and a color bit register, which store values that enable the node to resolve ordered transaction messages issued by the other nodes in a precise order, even though the nodes are operating independently, and receive the various transaction messages in totally different timing orders. Because the control logic is distributed among the nodes, no centralized controller is necessary.
Owner:DEGIRUM CORP
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