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2747results about How to "Avoid layering" patented technology

Thin-film deposition apparatus

A gas-feeding apparatus configured to be connected to an evacuatable reaction chamber includes a gas-distribution head for introducing gases into the chamber through a head surface. The gas-feeding head includes a first section for discharging a gas through the head surface toward a susceptor and a second section for discharging a gas through the head surface toward the susceptor. The first and the second sections are isolated from each other in the gas-distribution head, at least one of which section is coupled to an exhaust system for purging therefrom a gas present in the corresponding section without passing through the head surface.
Owner:ASM JAPAN

Versatile orthopaedic leg mounted walkers

A versatile orthopedic walker includes a high strength engineered plastic base with spaced upper and lower surfaces and upwardly extending slotted strut supports. The base may be laterally and vertically cored, and an outer sole is provided which extends upward over the core openings, with the upper edges of the outsole being ridged to fit into a peripheral groove in the base to provide a smooth exterior surface. Struts of different lengths are provided, and all of the struts have identical arrangements for interlocking with the base. All of the struts may be provided with a three pronged construction to triply lock the struts into the base. The struts may have areas of reduced cross-section providing pivot points or areas of flexibility to accommodate different size patients, and limiting stops may be provided to assure adequate orthopedic support. Fully integrally molded pivoting D-rings may hold walker straps in place.
Owner:OSSUR HF

Electroluminescent device

The electroluminescent device successively comprises a cathode, an electroluminescent layer, a transparent electrode layer, an evanescent light-scattering layer comprising a matrix composed of a low-refractive material containing light-scattering particles, and a transparent sheet / plate. Such an electroluminescent device is decreased in total reflection not only at a boundary surface between a transparent substrate and an outside air layer but also at a boundary surface of the transparent electrode layer on its light extraction side, and therefore, is considerably improved in light extraction efficiency. In addition, in the electroluminescent device provided with a barrier layer, the transparent electrode layer and the electroluminescent layer can be well protected so that deterioration of electroluminescent pigments and occurrence of dark spots can be effectively prevented, resulting in enhanced life of the device.
Owner:MITSUBISHI CHEM CORP

Patterning of and contacting magnetic layers

A method according to embodiments of the present invention comprises providing a magnetic stack comprising a magnetic layer sub-stack comprising magnetic layers and a bottom conductive electrode and a top conductive electrode electrically connecting the magnetic layer sub-stack at opposite sides thereof; providing a sacrificial pillar on top of the magnetic stack, the sacrificial pillar having an undercut with respect to an overlying second sacrificial material and a sloped foot with increasing cross-sectional dimension towards the magnetic stack, using the sacrificial pillar for patterning the magnetic stack, depositing an insulating layer around the sacrificial pillar, selectively removing the sacrificial pillar, thus creating a contact hole towards the patterned magnetic stack, and filling the contact hole with electrically conductive material.
Owner:INTERUNIVERSITAIR MICRO ELECTRONICS CENT (IMEC VZW) +1

Semiconductor device and method for fabricating the same

To provide a highly reliable semiconductor device exhibiting stable electrical characteristics. To fabricate a highly reliable semiconductor device. Included are an oxide semiconductor stack in which a first oxide semiconductor layer, a second oxide semiconductor layer, and a third oxide semiconductor layer are stacked, a source and a drain electrode layers contacting the oxide semiconductor stack, a gate electrode layer overlapping with the oxide semiconductor layer with a gate insulating layer provided therebetween, and a first and a second oxide insulating layers between which the oxide semiconductor stack is sandwiched. The first to the third oxide semiconductor layers each contain indium, gallium, and zinc. The proportion of indium in the second oxide semiconductor layer is higher than that in each of the first and the third oxide semiconductor layers. The first oxide semiconductor layer is amorphous. The second and the third oxide semiconductor layers each have a crystalline structure.
Owner:SEMICON ENERGY LAB CO LTD

Semiconductor device and production method thereof

A method of fabricating a semiconductor device is disclosed that is able to suppress a short channel effect and improve carrier mobility. In the method, trenches are formed in a silicon substrate corresponding to a source region and a drain region. When epitaxially growing p-type semiconductor mixed crystal layers to fill up the trenches, the surfaces of the trenches are demarcated by facets, and extended portions of the semiconductor mixed crystal layers are formed between bottom surfaces of second side wall insulating films and a surface of the silicon substrate, and extended portion are in contact with a source extension region and a drain extension region.
Owner:FUJITSU SEMICON LTD

Nonaqueous electrolyte secondary battery and method for manufacturing the same

A lithium ion secondary battery includes a positive electrode, a negative electrode, a porous insulating layer and a nonaqueous electrolyte. The porous insulating layer is provided between the positive electrode material mixture layer and the negative electrode material mixture layer and contains a material which does not have a shutdown function. The positive electrode is provided with a PTC layer extending substantially parallel to the positive electrode collector and the negative electrode is provided with a PTC layer extending substantially parallel to the negative electrode collector. Each of the PTC layers contains a material having a positive temperature coefficient of resistance.
Owner:PANASONIC CORP

Carrier-free semiconductor package and fabrication method thereof

A carrier-free semiconductor package and a fabrication method thereof are provided. The fabrication method includes the steps of: providing a carrier having a plurality of electrical contacts formed thereon; mounting at least one chip on the carrier; electrically connecting the chip to the electrical contacts via a plurality of bonding wires; forming a coating layer on each of the electrical contacts to encapsulate a bonded end of each of the bonding wires on the electrical contacts; performing a molding process to form an encapsulant for encapsulating the chip, the bonding wires and the electrical contacts; and removing the carrier, such that bottom surfaces of the electrical contacts are exposed from the encapsulant. This obtains a semiconductor package not having a carrier, and the coating layers can enhance adhesion between the electrical contacts and the encapsulant.
Owner:SILICONWARE PRECISION IND CO LTD
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