394 results about "Line resistance" patented technology

A method and apparatus for aggregating power from multiple sources generates a single direct current regulated voltage. The apparatus comprises a plurality of slave voltage converters and a master pulse width modulator circuit. Providing a plurality of direct current power sources, current is drawn through a plurality of lines connected to the plurality of direct current power sources. An open circuit voltage for each direct current power source is unknown. Each line of the plurality of lines has a line resistance. The line resistance of at least some of the plurality of lines may be unknown. The line resistance of at least some of the plurality of lines is large. The single direct current regulated voltage is generated from the drawn current.

At a writing time, a first transistor 412 is turned on so that a data signal Xj is supplied to one end of a capacitor 420. At this time, since a second transistor 414 is turned off, driving current does not flow to an organic light emitting diode (OLED) device 430. A power supply voltage Vdd is supplied to the other end of a capacitor through a power supply line L. However, since the driving current does not flow at the writing time, the power supply voltage Vdd is not reduced by the wiring line resistance of the power supply line L. On the other hand, at an emission time, the first transistor 412 is turned off and the second transistor 414 is turned on. Therefore, the driving current is supplied to the OLED device 430.

A three-dimensional array is especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. A two-dimensional array of bit lines to which the memory elements of all planes are connected is oriented vertically from the substrate and through the plurality of planes. During sensing, to compensate for word line resistance, a sense amplifier references a stored reference value during sensing of a memory element at a given location of the word line. A layout with a row of sense amplifiers between two memory arrays is provided to facilitate the referencing. A selected memory element is reset without resetting neighboring ones when it is subject to a bias voltage under predetermined conditions.

An electrically-driven liquid crystal lens wherein electric connection between finely split electrodes and signal lines used to apply signals to the split electrodes can be accomplished using a minimal number of masks and signals can be applied to the finely split electrodes without line resistance, and a stereoscopic display device using the same are disclosed. The liquid crystal lens includes first and second substrates arranged opposite each other and each defining a plurality of lens regions, a plurality of metal lines formed on the first substrate, a first insulating film formed on the first substrate, a plurality of first electrodes formed on the first insulating film in the respective lens regions to intersect the plurality of metal lines, a second insulating film formed on the first electrodes, a plurality of second electrodes formed on the second insulating film at positions alternating with the first electrodes, a first contact structure between the first electrodes and the metal lines using a transparent electrode pattern of the same layer as the second electrodes, a second contact structure between the second electrodes and the plurality of metal lines, a common electrode formed over the entire surface of the second substrate, and a liquid crystal layer filled between the first substrate and the second substrate.

The present invention provides a structure of a semiconductor device that realizes low power consumption even where increased in screen size, and a method for manufacturing the same. The invention forms an insulating layer, forms a buried interconnection (of Cu, Au, Ag, Ni, Cr, Pd, Rh, Sn, Pb or an alloy thereof) in the insulating layer. Furthermore, after planarizing the surface of the insulating layer, a metal protection film (Ti, TiN, Ta, TaN or the like) is formed in an exposed part. By using the buried interconnection in part of various lines (gate line, source line, power supply line, common line and the like) for a light-emitting device or liquid-crystal display device, line resistance is decreased.

In a block of non-volatile memory, bit line current increases with bit line voltage. For current sensing memory systems, average bit line current during a sensing operation need only exceed a certain threshold amount in order to produce a correct result. For the first word lines being programmed in a block, memory cells connected thereto see relatively low bit line resistances during verify operations. In the disclosed technology, verify operations are performed for these first programmed word lines with lower verify bit line voltages in order to reduce excess bit line current and save power. During read operations, this scheme can make threshold voltages of memory cells connected to the lower word lines appear lower. In order to compensate for this effect, various schemes are disclosed.

The present invention relates generally to detecting energy theft within an energy distribution system and more particularly to systems and methods for detecting energy discrepancies in voltages and / or currents reported by electric meters present in a distribution circuit, without requiring installation of additional hardware at the transformer. Typically, the location of each of at least two meters is determined with respect to a transformer. The line resistances within the distribution circuit are determined starting with a line resistance farthest from the transformer. Estimated line voltages are determined for at least one electric meter using the estimated line resistances, and the estimated voltages are compared to actual voltage readings for the at least one electric meter. The existence of line loss is determined based on this comparison.

A multi-primary color display device includes a unit pixel part, a plurality of data lines, a plurality of pads and a plurality of connection lines. The unit pixel part is disposed on a display area and includes at least four subpixels. The data lines extend in a first direction on display area, and are electrically connected to the subpixels. The pads are arranged in a second direction perpendicular to the first direction on a peripheral area surrounding the display area, and are electrically connected to a driving chip. The connection lines connect the data lines to the pads disposed on the peripheral area. Each of the connection lines has a same line resistance.

The present invention provides a structure of a semiconductor device that realizes low power consumption even where increased in screen size, and a method for manufacturing the same. The invention forms an insulating layer, forms a buried interconnection (of Cu, Au, Ag, Ni, Cr, Pd, Rh, Sn, Pb or an alloy thereof) in the insulating layer. Furthermore, after planarizing the surface of the insulating layer, a metal protection film (Ti, TiN, Ta, TaN or the like) is formed in an exposed part. By using the buried interconnection in part of various lines (gate line, source line, power supply line, common line and the like) for a light-emitting device or liquid-crystal display device, line resistance is decreased.

A light emitting display includes a substrate, a pixel area, a first power source line to supply a first power signal to each pixel on a first side of the pixel area, a second power source line to supply the first power signal to each pixel on a second side of the pixel area, and an impedance compensator for compensating a difference in a voltage drop between the first power source line and the second power source line. A voltage drop caused by line resistance that depends on the length of the first and second power source line that supply the first power signal to a lower and upper side of a pixel area, respectively, is equalized, thereby minimizing the voltage drop of the first power signal supplied to all pixels, and minimizing non-uniformity of brightness due to the voltage drop differences at each pixel.

The invention discloses a solar cell front side silver slurry doped with modified graphene and a manufacture method therefor. The solar cell front side silver slurry doped with the modified grapheme is prepared from the following raw materials in parts by weight: 0.1-5 parts of modified graphene, 88-91 parts of silver powder, 5-15 parts of organic binders, 0.1-5 parts of organic solvents and 1-3 parts of glass powder. The modified graphene is graphene with surface modification. The solar cell front side silver slurry doped with the modified graphene and the manufacture method therefor are mainly used for lowering series resistance of a solar cell, a fast silk screen is developed and is printed on a crystalline silicon, a silicon wafer SiNx passivation layer is penetrated after a high sintering operation process, and therefore the front side silver slurry which is good in ohmic contact is formed; silver and silicon contact resistance and line resistance are lowered, and photoelectric conversion efficiency is improved; the front side silver slurry disclosed in the invention has wide market prospects.

A memory device includes a plurality of blocks, with each block having a respective array of memory cells and respective local word lines. The memory device also includes a respective switching device coupled between each local word line and a common voltage node. A global word line driver controls the respective switching devices to turn on for respective local word lines in a row across the blocks including an accessed memory cell. Thus, the common voltage node is in the current path of the accessed memory cell with minimized layout area and resistance of the current path.

A plurality of metal interconnects incorporating a Group II element alloy for protecting the metal interconnects and method to form and incorporate the Group II element alloy are described. In one embodiment, a Group II element alloy is used as a seed layer, or a portion thereof, which decreases the line resistance and increases the mechanical strength of a metal interconnect. In another embodiment, a Group II element alloy is used to form a barrier layer, which, in addition to decreasing the line resistance and increasing the mechanical integrity, also increases the chemical integrity of a metal interconnect.

A flat panel display reduces the line resistance of a driving power supply line and prevents a voltage drop in the driving power supply line so as to obtain uniform resolution and luminance. The flat panel display includes a substrate, a display region formed on the substrate, the display region having a self-luminescent element and VDD lines that supply a driving potential power and / or a source current to the self-luminescent element. Further, a covering member for sealing the display region at least, the covering member being adhered to the substrate to face the substrate and a terminal region formed on one or more edges of the substrate, the terminal region having one or more driving power terminals are provided. In addition, a driving power supply line that connects the driving power terminals to the VDD lines of the display region and a bus conductive unit that is electrically connected to the driving power supply line are provided.

The invention provides polyamide6-graphene quantum dot / carbon nanotube anti-static fiber and preparation. According to the method, the molecular template effect of graphene quantum dots is utilized for being compounded with a carbon nanotube to form a self-assembled three-dimensional network structure first and then combined with a PA6 knitting state structure to form a dislocation effect to construct a conductive path, conductivity is improved on the condition of not losing a mechanical property of PA6 fiber, and meanwhile conductivity and the mechanical property of the PA fiber are promoted. Moreover, by means of compounding of the graphene quantum dots and the carbon nano tube and the self-assembled three-dimensional network structure, electronic transmission efficiency in the carbon nano tube is improved, a small quantity of GQD / CNT is added, conductivity of the fiber can be improved, and transparency is improved at the same time, which is beneficial for treatment technologies like dyeing in the fiber preparing process. By means of the traditional mature PA6 melt spinning technology, the high-strength and high-conductivity PA6-GQD / CNT composite fiber with tensile strength being 0.52-0.81 GPa and line resistance being magnitude 106 is prepared and can be applied to anti-static clothes, needle-punched carpet, filter felt, industrial non-woven fabric, medical supplies and the like.

An organic EL display device and a method for driving the organic EL display device that compensate for a decrease in voltage between the gate and source of a driving transistor caused by a source voltage drop caused by a power supply line resistance. An organic EL display device includes a data driver for receiving digital image data and applying the digital image data and data voltages corresponding to pixel circuits. Even when receiving the same digital image data, the data driver outputs different data voltages according to the positions of the pixel circuits. When the driving transistor is a P-type transistor, the data driver applies a data voltage higher than that applied to a remote pixel circuit to a pixel circuit near an external voltage source even when receiving the same digital data. When the driving transistor is an N-type transistor, the data driver applies a data voltage lower than that applied to a distant pixel circuit to a pixel circuit near an external voltage source even when receiving the same digital data.

The invention discloses a temperature measurement circuit, which includes a temperature sensor circuit, a constant current source and a first operational amplifier. The negative pole of the power line drawn from the second end and the positive pole of the sensing lead and the negative pole of the sensing lead drawn from the first and second ends of the temperature sensor respectively, the constant current source is connected to the positive pole of the power line of the temperature sensor circuit, and the positive and negative poles of the first operational amplifier The negative input end is respectively connected to the positive electrode of the sensing lead and the negative electrode of the sensing lead of the temperature sensor circuit, the output end outputs a voltage-temperature curve, and the negative electrode of the power line of the temperature sensor circuit is coupled to the ground. The invention adopts a four-wire system, so that the positive and negative input ends of the first operational amplifier are respectively connected to the positive electrode of the sensing lead and the negative electrode of the sensing lead of the temperature sensor circuit. The effect of wire resistance on the output result.

Improved methods of depositing copper seed layers in copper interconnect structure fabrication processes are provided. Also provided are the resulting structures, which have improved electromigration performance and reduced line resistance. According to various embodiments, the methods involve depositing a copper seed bilayer on a barrier layer in a recessed feature on a partially fabricated semiconductor substrate. The bilayer has a copper alloy seed layer and a pure copper seed layer, with the pure copper seed layer is deposited on the copper alloy seed layer. The copper seed bilayers have reduced line resistance increase and better electromigration performance than conventional doped copper seed layers. Precise line resistance control is achieved by tuning the bilayer thickness to meet the desired electromigration performance.

The present invention relates to a data signal distortion compensation method and circuit for liquid crystal display panels, which is a method and a circuit that utilize adjusting the linear increase of the opening time width of scanning signals. As the total electric charge amount of the capacitance supplied to one row of display units can be the same, the reflected brightness can be the same as well. Therefore, the present invention can obviously improve the uneven brightness phenomenon caused by the on-line resistance-capacitance effect of data, so as to improve the phenomenon that liquid crystal display panels are uneven in brightness.

A liquid crystal display and a method of driving the same is capable of for preventing a difference in brightness from occurring between horizontal line blocks. A liquid crystal display includes a liquid crystal display panel having liquid crystal cells arranged in a matrix pattern; at least one integrated circuit for driving the liquid crystal display panel; a supply line commonly connected to the at least one integrated circuit for applying drive signals to the at least one integrated circuit; and a signal-limiting part formed at an input terminal of the supply line, wherein the supply line has a higher resistance than the sum of the line resistances of the entire supply line.

This invention relates to one 2D displacement measurement method, which comprises the following steps: according to Wheatstone bridge circuit test principle to distribute the bridge resistance wire into direct or arc shape and the direct resistance wire is to test line displacement; the arc resistance wire is to test arc length change volume and then according to the relationship between arc length and radium to get test point rotary angle; through testing points in electrode coordinate displacement change to realize 2D displacement. The 2D displacement sensor comprises the test bridge line resistance wire and arc resistance wire fixed onto one structure around axis and it also comprises data transmission line.

Provided is an organic light emitting diode (OLED) display device including a substrate on a front side of the OLED display device that is coupled to an encapsulation substrate on the back side of the OLED display device. An interconnection line is disposed in a predetermined region of the encapsulation substrate corresponding to a portion of the substrate on which no interconnection lines are disposed. Alternatively, a common power supply line is disposed only on the encapsulation substrate. As a result, a dead space in a display region of the substrate can be reduced so that other lines can be disposed in an interconnection line region of the substrate, and the display region can be further expanded. Also, since a wide interconnection line can be disposed on the encapsulation substrate, line resistance is decreased and a voltage drop can be reduced.

A display substrate includes source lines, gate lines, an output pad part, a fan-out part and a first voltage line part. The source lines are in a display area. The gate lines cross the source lines. The output pad part is in a peripheral area surrounding the display area and is electrically connected to output terminals of a driving chip. The fan-out part is electrically connected between the output pad part and the source lines. The first voltage line part is inclined with respect to a central line of a chip area in which the driving chip is mounted toward opposite sides of the chip area to cross the fan-out part. Therefore, the line reactance of the fan-out part is decreased and the uniformity of the line resistance of the fan-out part is increased to improve image display quality.

Disclosed is a full color flat display panel by using an organic electro-luminescent(EL) device, a manufacturing method thereof and a driving circuit of the organic EL device, in particular, which includes first, second and third pixels, a plurality of first electrodes, and a plurality of second electrodes perpendicularly intersecting the first electrodes, in which each of the first, second and third light emitting pixels is arranged in each of intersecting positions of the first and second electrodes. Light emitting pixels are arranged to have different areas according to luminous efficiency so that a red light emitting area with relatively poorer efficiency is sized larger than a blue or green light emitting area thereby manufacturing an efficient full color organic EL display panel. Also, the influence from the line resistance in the anode lines and the cathode lines is reduced when a constant current is introduced into the device structured of the RGB array in order to realize the white light as full color. Thus, the voltage loss on the line resistance is prevented and the area ratio of the device is adjusted to make each of the RGB pixels for generating the white light have the similar value of drive voltage thereby minimizing power loss.

A method for manufacturing a thin film transistor substrate including forming bus lines by etching a surface of a substrate to form bus line patterns and filling the bus line patterns with a bus line metal; forming a semiconductor channel layer at one portion of a pixel area defined by the bus lines; and forming source-drain electrodes on the semiconductor channel layer, a pixel electrode extending from the drain electrode within the pixel area, and a common electrode parallel with the pixel electrode. The bus lines are formed as being thicker but the bus lines are buried in the substrate so that the line resistance can be reduced and the step difference due to the thickness of bus line does not affect the device.

The present invention provides a structure of a semiconductor device that realizes low power consumption even where increased in screen size, and a method for manufacturing the same. The invention forms an insulating layer, forms a buried interconnection (of Cu, Au, Ag, Ni, Cr, Pd, Rh, Sn, Pb or an alloy thereof) in the insulating layer. Furthermore, after planarizing the surface of the insulating layer, a metal protection film (Ti, TiN, Ta, TaN or the like) is formed in an exposed part. By using the buried interconnection in part of various lines (gate line, source line, power supply line, common line and the like) for a light-emitting device or liquid crystal display device, line resistance is decreased.

The invention belongs to the field of solar cells, and provides an electrode of a full-back-contact solar cell and a fabrication method of the electrode. The electrode is characterized in that the electrode comprises first fine grid metal electrodes, second fine grid metal electrodes, first main grid electrodes, second main grid electrodes and first dielectric layers, wherein the first fine grid metal electrodes, the second fine grid metal electrodes, the first main grid electrodes and the second main grid electrodes are positioned on a first main surface of a substrate; the first fine grid metal electrodes and the second fine grid metal electrodes are alternately distributed in an inter-digital shape; the first main grid electrodes and the second main grid electrodes are intersected with the first fine grid metal electrodes and the second fine grid metal electrodes respectively; intersected and overlapped parts between the first main grid electrodes and the second fine grid metal electrodes are isolated from intersected and overlapped parts between second first main grid electrodes and the first fine grid metal electrodes by the dielectric layers; and the first main grid electrodes and the first fine grid metal electrodes are directly contacted with the second main grid electrodes and the second fine grid metal electrodes in intersected and overlapped positions. Compared with the prior art, according to the electrode and the fabrication method, an influence of electrical shading of the electrode is eliminated; line resistance losses of the electrode are reduced; and the performance of a device is improved.

In a display substrate and a display device having the display substrate for reducing a line resistance, the display substrate includes a plurality of pixel parts, a signal line part and a signal pad part. The pixel parts are formed in a display area. The signal line part is formed in a peripheral area surrounding the display area. The signal line part includes a first line formed with a first conductive layer, and a second line formed with a second conductive layer over the first line. The second line overlaps the first line. The signal pad part includes a first pad integrally formed with the first line, and a second pad integrally formed with the second line, wherein an identical driving signal is applied to the first pad and the second pad. Accordingly, the line resistance of the signal line part may be reduced.

An FeRAM memory array wherein the plate lines run in the direction of word lines is described that provides a reduced plate line resistance in arrays having a common plate line connection. The lower plate line resistance reduces the magnitude of negative spikes on the plate line to reduce the potential for FeCap depolarization. Two or more plate lines of a plurality of columns of memory cells are interconnected along a bit line direction. Some or all of the plate lines of one or more columns of dummy memory cells may also be interconnected to reduce the plate line resistance and minimize any increase in the bit line capacitance for the active cells of the array. The improved FeRAM array provides a reduced data error rate, particularly at fast memory cycle times.