A
chip structure comprises a substrate, a first built-up layer, a
passivation layer and a second built-up layer. The substrate includes many
electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-up layer is provided with a first
dielectric body and a first
interconnection scheme, wherein the first
interconnection scheme interlaces inside the first
dielectric body and is electrically connected to the
electric devices. The first
interconnection scheme is constructed from first
metal layers and plugs, wherein the neighboring first
metal layers are electrically connected through the plugs. The
passivation layer is disposed on the first built-up layer and is provided with openings exposing the first interconnection scheme. The second built-up layer is formed on the
passivation layer. The second built-up layer is provided with a second
dielectric body and a second interconnection scheme, wherein the second interconnection scheme interlaces inside the second
dielectric body and is electrically connected to the first interconnection scheme. The second interconnection scheme is constructed from at least one second
metal layer and at least one via metal filler, wherein the second metal layer is electrically connected to the via metal filler. The thickness, width, and cross-sectional area of the traces of the second metal layer are respectively larger than those of the first metal
layers.