218results about How to "Reduce wire resistance" patented technology

The wireless power transmission system of this invention transmits power over a resonant magnetic field. The system includes a power-transmitting resonator 105 and a power-receiving resonator 107, at least one of which is a series resonant circuit with an inductor including spiral wiring 201 and extended wires 213, 207a, 207b and 207c. The extended wire 213 connects a point 203 of the spiral wiring 201 to a power supplying structure, while the extended wires 207a, 207b and 207c connect other points of the spiral wiring 201 to the power supplying structure. Capacitors 209a, 209b and 209c and switches 211a, 211b and 211c are connected to the extended wires 207a, 207b and 207c, respectively. The series resonant circuit has its inductance varied according to which current path has been chosen by selectively turning ON one of the switches. A wiring portion 201a of the spiral wiring 201 has a low-resistance portion 2010, of which the wiring resistance per unit length at a resonant frequency is set to be lower than in at least a part of the rest of the spiral wiring.

The silica film forming material of the present invention comprises a silicone polymer which comprises, as part of its structure, CHx, an Si—O—Si bond, an Si—CH₃ bond and an Si—CHx- bond, where x represents an integer of 0 to 2.

A microelectromechanical system includes a substrate, a transducer supported on the substrate and a conductor layer, which is also supported on the substrate and electrically connected to the transducer. The transducer includes a portion made of silicon or a silicon compound. The conductor layer is made of a refractory conductor, which includes, as its main ingredient, at least one element selected from the group consisting of copper, gold and silver. At least a portion of the conductor layer is located at an intermediate level between the silicon or silicon compound portion of the transducer and the substrate.

It is an object of the present invention to suppress an influence of voltage drop due to wiring resistance to make an image quality of a display device uniform. In addition, it is also an object of the present invention to suppress delay due to a wiring for electrically connecting a driving circuit portion to an input/output terminal to improve an operation speed in the driving circuit portion.

In the present invention, a wiring including copper for realizing lowered wiring resistance, subjected to microfabrication, is used as a wiring used for a semiconductor device and a barrier conductive film for preventing diffusion of copper is provided for a TFT as a part of the wiring including copper to form the wiring including copper without diffusion of copper into a semiconductor layer of the TFT. The wiring including copper is a wiring including a laminate film of at least a conductive film containing copper as its main component, subjected to microfabricaiton, and the barrier conductive film.

A capacitive touch panel has a plurality of first transparent electrodes and a plurality of second transparent electrodes on a transparent substrate. At crossing portions between the first and second electrodes, adjacent electrodes of the second electrodes have no interruption, and adjacent electrodes of the first electrodes are interrupted. An interlayer insulating film is disposed as an upper layer on the second electrodes, and a bridge electrode is disposed as an upper layer on the interlayer insulating film to connect interrupted portions of the first electrodes at the crossing portions. The material constituting the bridge electrode contains an element that is more susceptible to oxidation than elements contained in a material constituting the second electrodes. Constant voltage is applied to the first electrodes, and a pulse voltage having a low potential equal to or higher than the potential of the first electrodes is applied to the second electrodes.

The invention relates to a preparation method of a micro-bridge structured infrared detector, and a micro-bridge structure. The method comprises the steps that: a metal reflective layer and a sacrificial layer are sequentially deposited on an infrared detector readout circuit substrate; PI holes are etched on the sacrificial layer, wherein the PI holes are positioned at an out-leading electrode of the readout circuit; a deposition support layer, a thermo-sensitive layer and a protective layer are sequentially deposited on the sacrificial layer; through holes are prepared in the PI holes, and a contact hole is prepared on the protective layer; electrode layer metal is deposited on the protective layer, and U-shaped metals with bridge pier structures are filled in the PI holes and the through holes; and U-shaped metal structures are formed through photolithography and etching; photolithography and etching is carried out upon the electrode layer metal; a passivation layer is deposited on the surface of the device, and the passivation layer is subjected to photolithography and etching, such that a passivation layer pattern is formed; and sacrificial layer releasing is carried out, such that the micro-bridge structure is formed. According to the invention, a U-shape filling method is adopted, and Al is adopted as a filling material. Therefore, sputtering and depositing are easy, and etching is convenient. The heat insulation property of the detector is better than that of a copper filling process, and a CMP step is not needed.

A light emitting apparatus with high homogeneity in image quality is provided, which includes anodes 102 on an insulator 101, cathodes 107 orthogonal to the anodes 102, and EL layers 106 interposed between the anodes 102 and the cathodes 107, and auxiliary wirings 103 are electrically connected to the anodes 102. The auxiliary wirings 103 are made of a material lower in resistance than that of the anodes 102, thereby being capable of reducing the wiring resistance of the anodes 102.

The semiconductor device includes: a transistor having a gate electrode formed on a semiconductor substrate and first and second source/drain regions formed in portions of the semiconductor substrate on both sides of the gate electrode; a gate interconnect formed at a position opposite to the gate electrode with respect to the first source/drain region; and a first silicon-germanium layer formed on the first source/drain region to protrude above the top surface of the semiconductor substrate. The gate interconnect and the first source/drain region are connected via a local interconnect structure that includes the first silicon-germanium layer.

The invention relates to a capacitance type touch screen and a manufacturing method thereof. The capacitance type touch screen comprises a substrate, two sets of transparent conducting films of conducting wires, an insulating film and a metal bridging beam film. In the two sets of conducting wires, the first set of transparent conducting films are continuously arranged, and the second set of transparent conducting films are piecewise arranged by using the transparent conducting films of the first set as intervals. The insulating film covers the surfaces of the two sets of transparent conducting films, and the insulating film above each film section of the second set of transparent conducting films comprises a through hole. The metal bridging film is attached on the insulating film, crosses the first set of transparent conducting films and is connected with the second set of transparent conducting films which are arranged at intervals on both sides of the first set of transparent conducting films by passing through the through hole on the insulating film so as to form the continuous second conducting wires. The method comprises the following steps: manufacturing the first set of transparent conducting films, the second set of transparent conducting films, the insulating film and the metal bridging film to achieve the structure of the touch screen. The invention adopts the metal bridging film, thereby improving the continuity of the second set of conducting wires, reducing the resistance of the second set of conducting wires and the color difference of the touch screen and improving the performance of the touch screen and the product quality.

The present invention provides a flip-chip package substrate and a method for fabricating a flip-chip package substrate comprising a circuit build-up structure, which comprises at least a dielectric layer and at least a circuit layer, wherein each dielectric layer comprises a first surface and a second surface, plural vias are formed in the first surface, the circuit layer is formed on the first surface and in the vias to electrically connect to another circuit layer disposed under the dielectric layer; a metal layer embedded in the exposed second surface of the circuit build-up structure without protruding the exposed second surface and connected to the circuit layer; and two solder masks disposed on the exposed first surface and the exposed second surface of the circuit build-up structure, wherein the solder masks have plural openings to separately expose part of the circuit layer and the metal layer functioning as conductive pads.

To provide an electric power steering apparatus in which it is possible to minimize a connection distance between a control unit and an electric motor and surely prevent electric noise from mixing between the control unit and the electric motor as well as to minimize electric resistance and minimize an electric loss by directly connecting the control unit and connection terminals of the electric motor and a torque sensor. A motor control apparatus includes a steering column 3 having inserted therein a steering shaft 2 to which steering torque is transmitted, a reduction gear box 4 coupled to the steering shaft 2, and an electric motor 5 that transmits a steering assisting force to the steering shaft 2 via a reduction mechanism in the reduction gear box 4. The electric motor 5 and a control unit 19 including a control board mounted with a control circuit that controls to drive the electric motor 5 are provided side by side in the reduction gear box 4 and a connection terminal of the electric motor 5 is electrically connected to the control unit 19 directly.

Disclosed herein is a method of manufacturing a semiconductor device, including the steps of: forming an interlayer insulating film on a semiconductor substrate; forming a metal mask on the interlayer insulating film; forming a pattern trench in the metal mask and the interlayer insulating film by etching away parts of the metal mask and the interlayer insulating film; forming a conductive layer on the interlayer insulating film so as to fill in the pattern trench; and polishing the excessive conductive layer and the metal mask on the interlayer insulating film so as to leave the conductive layer in the pattern trench.

A multi-layered complementary wire structure and a manufacturing method thereof are disclosed, comprising a first wire and a second wire. Each of the first and the second wires comprises a main line and a plurality of branch lines located in a different layer from the main line. A plurality contact holes are formed in an insulating layer between the first wire and the second wire to connect the main line of the first wire and the branch lines of the first wire, and connect the main line of the second wire and the branch lines of the second wire. The main line of the first wire is insulated and crossed with the main line of the second wire. The main line of the first wire and the branch lines of the second wire are insulated with each other and located in the same layer. The main line of the second wire and the branch lines of the first wire are insulated with each other and located in the same layer.

There is provided a display device comprising a plurality of active elements on a substrate, a first insulating film for covering the active elements, electroconductive films were separated for each pixel on the first insulating film, a light-emitting layer disposed in an upper layer of the electroconductive films, and a common electrode disposed in an upper layer of the light-emitting layer, wherein a structure is used in which the electroconductive films have a layered film of a first electroconductive film, second electroconductive film, and third electroconductive film; the first electroconductive film is composed of ITO or chromium; the second electroconductive film is composed of aluminum with alumina on a surface; the second electroconductive film covers outside edges of the first electroconductive film; the third electroconductive film is composed of ITO; and the first electroconductive film and third electroconductive film are caused to contact each other.

A plurality of wires and electrodes are formed by forming a first conductive film, selectively forming a resist over the first conductive film, forming a second conductive film over the first conductive film and the resist, removing the second conductive film formed over the resist by removing the resist, forming a third conductive film so as to cover the second conductive film formed over the first conductive film, and selectively etching the first conductive film and the third conductive film. Thus, wires using a low resistance material can be formed in a large-sized panel, and thus, a problem of signal delay can be solved.

A semiconductor device comprises a plurality of semiconductor pillars laid out in matrix in a first and a second directions parallel with a main surface of a semiconductor substrate, and extending to a direction substantially perpendicular to the main surface; gate insulating films covering each surface of the plurality of semiconductor pillars, respectively; upper diffusion layers formed in each upper part of the plurality of semiconductor pillars, respectively; lower diffusion layers formed in each lower part of the plurality of semiconductor pillars, respectively; gate electrodes encircling at least each channel region between each upper diffusion layer and each lower diffusion layer, respectively; and a plurality of lower electrodes short-circuiting the lower diffusion layers adjacent in the first direction.

A semiconductor integrated device includes a plurality of power system circuit units, a first circuit unit 101 to which electric power is supplied from first power supply wiring 106, and first ground wiring 109 to which the first circuit unit is coupled. Moreover, the semiconductor integrated device includes a second circuit unit 102 to which electric power is supplied from second power supply wiring 113, and second ground wiring 116 coupled to the second circuit unit.

The first circuit unit includes a first interface circuit unit 104, and the second circuit unit includes a second interface circuit unit 111 configured to perform inputting or outputting of a signal to and from the first interface circuit unit. The first ground wiring is coupled to the second ground wiring through a protection circuit 117, and the second interface circuit unit is placed in the vicinity of the first interface circuit unit.

A display unit includes, on an insulating substrate, a plurality of wirings formed to extend in different directions, a thin-film transistor, and a display element. At least one of the plurality of wirings is a divided wiring having a crossing portion formed at an intersection with the other of the plurality of wirings, and a main portion which is formed in a layer same as the other of the plurality of wirings with an insulating film in between and which is electrically connected to the crossing portion via an conductive connection provided in the insulating film. At least one of the main portion and the crossing portion includes a first layer and a second layer stacked in order from the insulating substrate side, the second layer being in direct contact with the first layer and made of a material of a higher melting point than the first layer.

The invention relates to a TFT-LCD array substrate structure and a preparation method thereof. The TFT-LCD array substrate structure comprises gate lines and data lines which define a pixel area; thinfilm transistors are formed at crossing positions of the gate lines and the data lines, and are connected with pixel electrodes formed in the pixel area; waved bases used for forming the gate lines and/or the data lines are formed between the gate lines or the data lines and a substrate; the shape of the cross section of each waved base along the width direction is waved; and the gate lines and/or data lines formed on the waved bases are waved gate lines and/or waved data lines. The TFT-LCD array substrate structure can reduce the line resistance of the gate lines and/or the data lines, is favorable for reducing signal delay, and cannot reduce the aperture ratio of a TFT-LCD; or the aperture ratio of the TFT-LCD can be increased to improve product performance while the critical dimensionof the gate lines or the data lines is maintained.

Example embodiments relate to a wiring structure, a method of forming the same, and an electronic device employing the same. The wiring structure includes a first conductive material layer and a nanocrystalline graphene layer on the first conductive material layer in direct contact with the metal layer.

The invention provides a display system with a capacitive touch panel and a manufacturing method thereof. The display system with a capacitive touch panel comprises a substrate, an electrode circuit, a plurality of signal lines, a dielectric layer and an electrode bridging structure, wherein the electrode circuit is provided with a first electrode and a second electrode, the first electrode comprises a plurality of first conductive patterns, the second electrode comprises a plurality of second patterns, and the first conductive patterns are mutually electrically connected; the plurality of signal lines are formed on the substrate; the dielectric layer is formed on the electrode circuit and covers the electrode circuit; and in the invention, the electrode bridging structure with uniform thickness is formed on the dielectric layer by using a metal open repair technique, so that the second patterns are mutually electrically connected.

A flexible circuit board includes a base substrate, a driving chip, an input transmission line, an output transmission line and a connecting transmission line. The driving chip is on a surface of the base substrate. The input transmission line is on the surface of the base substrate and electrically connected to an input terminal of the driving chip. The output transmission line is on the surface of the base substrate and electrically connected to an output terminal of the driving chip. The input transmission line is electrically connected to the output transmission line through the connecting transmission line.

The method of manufacturing a piezoelectric actuator, includes the steps of: forming a lower electrode film on an insulating substrate; forming a piezoelectric film on the lower electrode film; forming a slit on the piezoelectric film to expose a portion of the lower electrode film on an upper surface side of the piezoelectric film; forming an insulating layer which covers a portion of the piezoelectric film; forming an upper electrode film so as to span the insulating layer and the piezoelectric film; forming, on the piezoelectric film, a lower wire in connection with the portion of the lower electrode film exposed through the slit; depositing a first metal film on the lower wire and thereby making a film thickness of the lower wire greater than a film thickness of the lower electrode film; and depositing a second metal film on a portion of the upper electrode film on the insulating layer and thereby making a film thickness of the portion of the upper electrode film on the insulating layer greater than a film thickness of a portion of the upper electrode film that has been deposited directly on the piezoelectric film.

An ink jet head circuit board is provided which has heaters to generate thermal energy for ejecting ink as they are energized. This circuit board is so constructed as to reduce wire resistances for the heaters while at the same time preventing an increase in the size of the board and realizing a high-density integration of the heaters required for high resolution printing. This construction is made possible by forming electrode wires of first and second electrode wire layers to reduce an area that the wire patterns for the heater occupy on the circuit board. In reducing the effective thickness of protective insulation layer formed on the heater to prevent a possible degradation of thermal efficiency, one of the protective insulation layers over the electrode wires is removed from the heater, depending on the thickness of the electrode wires.

Solar cell including: a semiconductor substrate of a first conductivity type having a region of the first conductivity type and region of a second conductivity type on the back side; a first finger electrode composed of a first contact portion and first current collector, a second finger electrode composed of a second contact portion and second current collector, a first bus bar electrode, a second bus bar electrode on the backside; an insulator film disposed at least in the area just under the first bus bar electrode and second bus bar electrode; wherein the electrical contact between the first current collector and first bus bar electrode as well as electrical contact between the second current collector and the second bus bar electrode are made on the insulator film; and first contact portion and the second contact portion are in a continuous line shape at least just under the insulator film.

A liquid ejecting head and a method of manufacturing the liquid ejecting head are provided. The liquid ejecting head has a pressure chamber forming substrate that includes a plurality of piezoelectric elements and that is connected to a first surface of a sealing plate, a driver IC that outputs signals that drive the piezoelectric elements and that is provided on a second surface of the sealing plate that is on the opposite side to the first surface, and a power supply wire that supplies electrical power to the piezoelectric elements, that is formed in the second surface of the sealing plate, and that has at least one portion thereof embedded in the sealing plate and a surface thereof exposed on the second surface side.