2366 results about "Solder mask" patented technology

An object of the present invention is to provide a substrate for mounting an IC chip which is a component for optical communication having an IC chip and an optical component integrally provided thereon, which can ensure a short distance between the IC chip and the optical component, which is excellent in electric signal transmission reliability and which can transmit optical signal through an optical path for transmitting optical signal. The substrate for mounting an IC chip of the present invention is a substrate for mounting an IC chip comprising: a substrate and, as serially built up on both faces thereof, a conductor circuit and an interlaminar insulating layer in an alternate fashion and in repetition; a solder resist layer formed as an outermost layer; and an optical element mounted thereto, wherein an optical path for transmitting optical signal, which penetrates the substrate for mounting an IC chip, is disposed.

A pillar-to-pillar flip-chip assembly primarily comprises a substrate, a chip disposed on the substrate, a plurality of first copper pillars on the bonding pads of the chip, a plurality of second copper pillars on the bump pads of the substrate, and a soldering material. A first height of the first copper pillars protruding from the active surface of the chip is the same as a second height of the second copper pillars from the solder mask on the substrate. When the soldering material electrically and mechanically connects the first copper pillars to the second copper pillars, a plurality of central points of the soldering material are formed on an equal-dividing plane between the chip and the substrate to reduce the direct stresses exerted at the soldering material to avoid peeling or breaks from the bump pads. Moreover, each of conventional solder balls is replaced with two soldered copper pillars to meet the lead-free requirements with higher reliability and lower costs.

A ball grid array package comprises a substrate having a first surface and a second surface, a chip, an insulating material, and a solder ball. The surface of the substrate comprises ball pads, conducting traces, and solder masks wherein the conducting traces are disposed in between the adjacent ball pads, and are covered by the solder mask, in addition, a portion of each of the ball pads is also covered by the solder mask. The solder mask includes an opening positioned in the area corresponding to the ball pads wherein the opening exposes a portion of the surface the ball pad and a portion of the side wall of the ball pad. The chip is disposed on the second surface of the substrate, and is sealed and encapsulated by the insulated material. The solder balls are disposed on the first surface of the substrate, and are positioned at the openings of the ball pads. Additionally, the solder balls are electrically connected to a portion of the surface of the ball pads and a portion of the side wall of the ball pads disposed at the ball pad openings.

In accordance with the present invention, a built-up bump pad structure and method for the same are provided. The bump pad structure includes a substrate, a bump pad disposed upon the substrate, a solder mask disposed upon the substrate defining an opening around the bump pad, and a conductive material deposited upon the bump pad such that the conductive material at least partially fills the opening around the bump pad.

A substrate structure of Flip Chip package includes a plurality of patterned circuit layers alternately stacking up with at least an insulative layer for isolating the patterned circuit layers. The patterned circuit layers are electrically connected each other wherein one of the patterned circuit layers is positioned on the surface of the substrate. The patterned circuit layer includes a plurality of first mounting pads and a plurality of second mounting pads. The solder mask layer covers the patterned circuit layer on the surface of the substrate, and a portion of the surface of the outer edge of the mounting pads while exposes a portion of the surface of the first mounting pads and the whole surface of the second mounting pads.

A carrier for use in a semiconductor die package is disclosed. In one embodiment, the carrier includes a die attach region and an edge region. A solder mask is on the edge region.

A package substrate, including a base layer, a surface circuit layer, a plurality of conductive bumps, and a patterned solder mask layer, is provided. The surface circuit layer having a plurality of bonding pads is disposed on a surface of the base layer. The conductive bumps are disposed on the bonding pads individually. The patterned solder mask layer is disposed on the surface of the base layer and outside a corresponding region occupied by the conductive bumps, so as to expose the conductive bumps. In addition, a method of fabricating the package substrate and a chip package structure employing the package substrate are also provided.

A solderable device includes a substrate and a soldering pad overlying the substrate. A solder mask overlies the substrate and portions of the soldering pad. The solder mask has an opening that exposes a portion of the soldering pad. The opening has at least two edges that symmetrically overlie portions of the soldering pad.

In one embodiment, an integrated circuit package includes a die associated with an integrated circuit and a die pad. The die has a bottom surface, and the pad has a top surface opposite the bottom surface of the die. Two or more bump pad traces are each coupled to the top surface of the pad, and one or more other traces are each coupled to the top surface of the pad in a corresponding inter-bump pad region between adjacent bump pad traces. A number of solder bumps each couple the die to the pad at a corresponding bump pad trace to provide electrical connectivity between circuitry associated with the die and circuitry associated with the die pad. Each inter-bump pad region is free from any solder mask material deposited to control collapse of the die towards the pad during a reflow process for bonding the die to the pad using the bumps, a supporting structure that contacts the die during the reflow process having been used instead.

A chip package includes a chip, a carrier, and at least a bump connecting structure for connecting the chip to the carrier. The bump connecting structure includes a first metal bump disposed on a chip pad of the chip and has a first height relative to a passivation layer of the chip, a second metal bump disposed on a carrier pad of the carrier and has a second height relative to a solder mask layer of the carrier, and a middle metal part disposed between the first and the second metal bumps. The sum of the minimum distance between the first and the second metal bumps, the first height of the first metal bump, and the second height of the second metal bump is less than 60 micrometers. The melting point of the middle metal part is lower than that of the first and the second metal bumps.

A substrate for solder joint is provided, including: a core layer; at least one conductive trace formed on the core layer and having a circular terminal as a pad through which a plurality of hollow portions are formed and expose predetermined portions of the core layer underneath the pad, wherein the hollow portions are arranged at equal intervals and spaced from a periphery of the circular pad; and a solder mask for covering the conductive trace and having at least one opening bordered across each of the hollow portions of the pad, such that part of the pad and part of each of the predetermined portions of the core layer are exposed via the opening, to allow a conductive element to be bonded to the exposed part of the pad and the exposed part of the predetermined portions of the core layer in the opening of the solder mask.

A light emitting apparatus (8) includes one or more light emitting chips (10) that are disposed on a printed circuit board (12) and emit light predominantly in a wavelength range between about 400 nanometers and about 470 nanometers. The printed circuit board includes: (i) an electrically insulating board (14); (ii) electrically conductive printed circuitry (20); and (iii) an electrically insulating solder mask (22) having vias (24) through which the one or more light emitting chips electrically contact the printed circuitry. The solder mask (22) has a reflectance of greater than 60% at least between about 400 nanometers and about 470 nanometers.

A flip-chip (FC) package structure is provided. The FC package structure includes a substrate, a chip, a plurality of copper platforms, a plurality of copper bumps, a plating layer, a circuit layer and a solder mask layer. The copper bumps are disposed on the substrate. The copper platforms are stacked on the copper bumps. The plating layer covers the copper bumps and the copper platforms, for contacting with chip foot pads configured at a bottom of the chip. The FC package structure does not need to reserve a space for wire bonding, thus saving the area of the substrate. The copper platforms are stacked on the copper bumps, and are higher than the circuit pattern layer. Therefore, the chip is blocked up, and the gap between the chip and the substrate is enlarged, thus preventing the risk of configuring voids when filling the cladding material and improving the packaging yield.

A wrist-worn device monitors movements of a user. A curvilinear body of the wrist-worn device includes a plurality of flex areas, and an internal spine member of the wrist-worn device extends through the curvilinear body. A flexible circuit member is wrapped around and connected to the spine member. The flexible circuit member interconnects a controller and one or more sensors of a sensor assembly within the body. A solder mask applied to the flexible circuit member includes a curvilinear edge that distributes stress caused by flexing of the flexible circuit member.

A single wiring layer is formed on each of both the roughened surfaces of a core substrate by a semiadditive method. The wiring layers formed on the surfaces of the core substrate are electrically connected through a through hole formed in the core substrate. The through hole is formed in the core substrate by laser machining. The through hole is filled up with conductive a plug. Both the surfaces of the core substrate are coated with solder resist layers, respectively, with predetermined terminal parts of the wiring layers exposed through openings formed in the solder resist layers. End surfaces of the conductive plug filling up the through holes, and the surfaces of the wiring layers are planarized by mechanical or chemical-mechanical polishing.

A ball grid pad for connecting a ball grid array package to a printed circuit board includes a circular pad area adhered on a ball grid connection surface. A solder mask on the ball grid connection surface has an opening surrounding and spaced apart from the circular pad area. The ball pad includes an anchor trace on the ball grid connection surface wherein the ball pad conductor material extends radially from the edge of the circular pad area to a terminating point beyond the opening of the solder mask so that a portion of the anchor trace is covered by the solder mask. The ball grid connection surface may be an integrated circuit package substrate or a printed circuit board surface.

A chip package includes a chip, a carrier, and at least a bump connecting structure for connecting the chip to the carrier. The bump connecting structure includes a first metal bump disposed on a chip pad of the chip and has a first height relative to a passivation layer of the chip, a second metal bump disposed on a carrier pad of the carrier and has a second height relative to a solder mask layer of the carrier, and a middle metal part disposed between the first and the second metal bumps. The sum of the minimum distance between the first and the second metal bumps, the first height of the first metal bump, and the second height of the second metal bump is less than 60 micrometers. The melting point of the middle metal part is lower than that of the first and the second metal bumps.

A thermally enhanced semiconductor package and a fabrication method thereof are provided. A plurality of conductive bumps are formed on bond pads on an active surface of a chip. A heat sink is attached to an inactive surface of the chip and has a surface area larger than that of the chip. An encapsulation body encapsulates the heat sink, chip and conductive bumps, while exposing a bottom or surfaces, not for attaching the chip, of the heat sink and ends of the conductive bumps outside. A plurality of conductive traces are formed on the encapsulation body and electrically connected to the ends of the conductive bumps. A solder mask layer is applied over the conductive traces and formed with a plurality of openings for exposing predetermined portions of the conductive traces. A solder ball is implanted on each exposed portion of the conductive traces.

A bonding pad with high bonding strength to a solder ball and a bump includes a carrier, a wiring layer formed on the carrier, a protection layer formed on top of the wiring layer and a solder mask layer surrounded around the protection layer and the wiring layer to form a bonding pad opening. The protection layer is extended outside the bonding pad opening such that when solder are extended into the bonding pad opening, the solder balls engage with side faces defining the bump pad opening as well as the protection layer outside the bump pad opening and a bonding strength between the bonding pad and the solder performance is increased.

A flip chip substrate structure and a method to fabricate thereof are disclosed. The structure comprises a build up structure, a first solder mask and a second solder mask. Plural first and second electrical contact pads are formed on the first and second surface of the build up structure, respectively. A first solder mask having plural openings is formed on the first surface of the build up structure, and the openings expose the first electrical contact pads, wherein the aperture of the openings of the first solder mask are equal to the outer diameter of the first electrical contact pads. A second solder mask having plural openings is formed on the second surface of the build up structure, and the openings expose the second electrical contact pads, wherein the aperture of the openings of the second solder mask are smaller than the outer diameter of the second electrical contact pads.

The invention is directed to a semiconductor device having a penetrating electrode and a manufacturing method thereof in which reliability and a yield of the semiconductor device are enhanced. A refractory metal layer is formed on a pad electrode formed on a semiconductor substrate with a first insulation film therebetween. Next, a passivation layer is formed on a front surface of the semiconductor substrate including on the pad electrode and on the refractory metal layer, and a supporting body is further formed with a resin layer therebetween. Next the semiconductor substrate is etched to form a via hole from a back surface of the semiconductor substrate to the pad electrode. Next, a penetrating electrode electrically connected with the pad electrode exposed at a bottom of the via hole and a wiring layer 21 are formed with a second insulation film therebetween. Furthermore, a solder resist layer and a conductive terminal are formed. Finally, the semiconductor substrate is cut and separated into semiconductor dies by dicing.

A substrate structure is provided. A plurality of solder pads is positioned on a substrate. A solder mask covers the substrate and has a plurality of openings to respectively expose portions of the solder pads, wherein the openings have the shape of a polygon of at least five sides.

The present application provides a latent ink-jet ink formulation suitable as solder mask. The composition generally comprises: (a) at least one compound capable of self cross-linking (USM); (b) at least one phenolic resin; (c) at least one solvent; (d) at least one mineral filler; (e) at least one polyol; and (f) at least one photoinitiator.

This invention improves reliability of a semiconductor device and a manufacturing method thereof. A glass substrate is bonded on a surface of a silicon wafer formed with pad electrodes. Next, via holes are formed from a back surface of the silicon wafer to pad electrodes, and a groove is formed extending along a center line of a dicing line and penetrating the silicon wafer from its back surface. After then, in processes including heating treatment, cushioning pads, wirings, a solder mask, and solder balls are formed on the back surface of the silicon wafer. Finally, the silicon wafer bolstered by the glass substrate is separated into individual silicon dice by dicing.

A first glass substrate is bonded through a resin to a top surface of a semiconductor wafer on which a first wiring is formed. A second glass substrate is bonded to a back surface of the semiconductor wafer through a resin. A V-shaped groove is formed by notching from a surface of the second glass substrate through a part of the first glass substrate. A second wiring connected with the first wiring and extending to the surface of the second glass substrate is formed. A protection film composed of an organic resin and a photoresist layer to provide the protection film with an opening are formed on the second wiring by spray coating. A conductive terminal is formed by screen printing using the protection film as a solder mask. A cushioning material may be formed on the second glass substrate by spray coating.