212results about How to "Improve reliability and performance" patented technology

A thermodynamic system that produces mechanical, electrical power, and / or fluid streams for heating or cooling. The cycle contains a combustion system that produces an energetic fluid by combustion of a fuel with an oxidant. A thermal diluent may be used in the cycle to improve performance, including but not limited to power, efficiency, economics, emissions, dynamic and off-peak load performance, and / or turbine inlet temperature (TIT) regulation and cooling heated components. The cycle preferably includes a heat recovery system and a condenser or other means to recover and recycle heat and the thermal diluent from the energetic fluid to improve the cycle thermodynamic efficiency and reduce energy conversion costs. The cycle may also include controls for temperatures, pressures, and flow rates throughout the cycle, and controls power output, efficiency, and energetic fluid composition.

A method of forming an integrated circuit interconnect structure is presented. A first conductive line is formed over a semiconductor substrate. A conductive cap layer is formed on the first conductive line to improve device reliability. An etch stop layer (ESL) is formed on the conductive cap layer. An inter-level dielectric (IMD) is formed on the ESL. A via opening and a trench are formed in the ESL, IMD, and conductive cap layer. A recess is formed in the first conductive line. The recess can be formed by over etching when the first dielectric is etched, or by a separate process such as argon sputtering. A second conductive line is formed filling the trench, opening and recess.

A method and circuit for implementing a chip to chip calibration in a chip stack, for example, with through silicon vias (TSV) stack, and a design structure on which the subject circuit resides are provided. A first chip and a second chip are included within a semiconductor chip stack. The semiconductor chip stack includes a vertical stack optionally provided with Though Silicon Via (TSV) stacking of the chips. At least one of the first chip and the second chip includes a calibration control circuit and a performance indicator circuit coupled to the calibration control circuit to train and calibrate at least one of the first chip and the second chip to provide enhanced performance and reliability for the semiconductor chip stack.

A method of estimating a deterioration state of a memory device comprises reading data from selected memory cells connected to a selected wordline of a memory cell array by applying to the selected wordline a plurality of distinct read voltages having values corresponding to at least one valley of threshold voltage distributions of the selected memory cells, generating quality estimation information indicating states of the threshold voltage distributions using the data read from the selected memory cells, and determining a deterioration state of a storage area including the selected memory cells based on the generated quality estimation information.

The invention provides an input device of the electronic cipher code lock and a corresponding input method thereof, wherein a signal device produces cipher code input information and converts said information into two groups of electrical pulse signals; a measurement and control device measures the electrical pulse signals, decides the order of the electrical pulse signals and calculates correspondingly such that said signals are converted into character sequences including the cipher code elements, and decides whether the current cipher code elements are confirmed to be inputted or not and decides whether the input of all the cipher code elements is completed or not; a confirmation device produces a conformation signal for inputting the cipher code elements; and a display device displays said character sequences and preset prompt information in a rolling and refreshing manner. The invention also provides a door lock handle and a panel of the cipher code lock for the chests and bags applying the above said input device of the electronic cipher code lock. In said input device of the electronic cipher code lock and the application thereof, the operation parts do not contact with the circuit, the reliability and the security protection performance have been improved significantly. Furthermore, the operation for inputting the cipher code and the operation for changing the cipher code are very convenient and intuitional.

A semiconductor device includes a substrate of a first conductivity type, an insulating layer formed on at least a portion of the substrate, and an epitaxial layer of a second conductivity type formed on at least a portion of the insulating layer. First and second source / drain regions of the second conductivity type are formed in the epitaxial layer proximate an upper surface of the epitaxial layer, the first and second source / drain regions being spaced laterally from one another. A gate is formed above the epitaxial layer proximate the upper surface of the epitaxial layer and at least partially between the first and second source / drain regions. The device further includes a first source / drain contact formed through the epitaxial layer and insulating layer, the first source / drain contact configured so as to be in direct electrical connection with the substrate, the first source / drain region and the epitaxial layer, and a second source / drain contact formed through the epitaxial layer, the second source / drain contact configured so as to be in direct electrical connection with the second source / drain region.