46513results about "Cooling/ventilation/heating modifications" patented technology

A power subsystem is actively optimized to improve total subsystem efficiency in a way that is responsive to changes in load requirements, power supply variations, and subsystem temperature variations. Detailed, multidimensional power loss models are developed for constituent devices which are then combined into a power subsystem containing a controller and circuity for measuring device operating parameters such as input and output voltage, output current, and temperature. Operating parameters are continually monitored, and set points are correspondingly changed based on the detailed power loss models to achieve maximum overall efficiency for the instantaneous operating state of the system.

Provided is a display apparatus including a display panel for displaying an image, a heat source arranged at a side surface of at least one side of the display panel, a heat absorbing section for absorbing heat generated by the heat source, a back surface plate arranged at a back surface side of the display panel and made of a metal, a portion of the back surface plate being in close contact with the heat absorbing section, a front surface plate arranged at a front surface side of the display panel and made of a metal, and a middle chassis arranged between the front surface plate and the heat absorbing section.

A motor control apparatus includes a steering column having inserted therein a steering shaft to which steering torque is transmitted, a reduction gear box coupled to the steering shaft, and an electric motor that transmits a steering assisting force to the steering shaft via a reduction mechanism in the reduction gear box. The electric motor and its control unit including a control board mounted with a control circuit, are provided side by side in the reduction gear box. A connection terminal of the electric motor is electrically connected to the control unit directly. This minimizes a connection distance between the control unit and the electric motor.

An electronic device includes an upper cover, a lower cover combined with the upper cover, and a heat conducting pillar. An accommodating space is formed by the upper cover and the lower cover. The heat conducting pillar is disposed in the accommodating space and physically connected with the upper cover and the lower cover to balance the temperature of the upper cover and the lower cover.

A novel massively parallel supercomputer of hundreds of teraOPS-scale includes node architectures based upon System-On-a-Chip technology, i.e., each processing node comprises a single Application Specific Integrated Circuit (ASIC). Within each ASIC node is a plurality of processing elements each of which consists of a central processing unit (CPU) and plurality of floating point processors to enable optimal balance of computational performance, packaging density, low cost, and power and cooling requirements. The plurality of processors within a single node may be used individually or simultaneously to work on any combination of computation or communication as required by the particular algorithm being solved or executed at any point in time. The system-on-a-chip ASIC nodes are interconnected by multiple independent networks that optimally maximizes packet communications throughput and minimizes latency. In the preferred embodiment, the multiple networks include three high-speed networks for parallel algorithm message passing including a Torus, Global Tree, and a Global Asynchronous network that provides global barrier and notification functions. These multiple independent networks may be collaboratively or independently utilized according to the needs or phases of an algorithm for optimizing algorithm processing performance. For particular classes of parallel algorithms, or parts of parallel calculations, this architecture exhibits exceptional computational performance, and may be enabled to perform calculations for new classes of parallel algorithms. Additional networks are provided for external connectivity and used for Input / Output, System Management and Configuration, and Debug and Monitoring functions. Special node packaging techniques implementing midplane and other hardware devices facilitates partitioning of the supercomputer in multiple networks for optimizing supercomputing resources.

A system includes a substantially sealed, substantially airtight cabinet sized for housing a vertical array of heat-producing units, the cabinet having an exterior shell and the system including an interior divider wall disposed inside the cabinet, the shell and divider wall providing an equipment chamber adapted to support the array such that the array cooperates with the shell and divider wall in use to define a first plenum, the first plenum having a first inlet defined by the divider wall for receiving a flow of cooling gas and having a first outlet defined by a plurality of openings through the array whereby the first plenum communicates with the openings in use to exhaust substantially all of the flow of cooling fluid through the openings and hence through the array, wherein the divider wall is configured to allow the first inlet to admit the gas to the first plenum in a substantially horizontal direction.

Method and apparatus are provided for thermally coupling one or more electronic devices to a heatsink. The apparatus comprises a heatsink having a substantially planar upper surface, a wiring board (PWB) with a through-hole for receiving the device such that a principal face thereof is in thermal contact with the heatsink, its electrical leads are captured between at least a portion of the wiring board and the heatsink, and a top of the device protrudes through the PWB. The method comprises placing the device in the through-hole with its base exposed on and protruding from the underside of the PWB, attaching its electrical leads to contacts on the wiring board and pressing the PWB toward the heatsink with the leads captured there between. An electrically insulating thermally conducting layer is desirably placed between the wiring board and the heatsink.

System-in packages, or multichip modules, are described which can include multi-layer chips and multi-layer dummy substrates over a carrier, multiple through vias blindly or completely through the multi-layer chips and completely through the multi-layer dummy substrates, multiple metal plugs in the through vias, and multiple metal interconnects, connected to the metal plugs, between the multi-layer chips. The multi-layer chips can be connected to each other or to an external circuit or structure, such as mother board, ball grid array (BGA) substrate, printed circuit board, metal substrate, glass substrate, or ceramic substrate, through the metal plugs and the metal interconnects.

Apparatus and methods according to the present invention preferably utilize electroosmotic pumps that are capable of generating high pressure and flow without moving mechanical parts and the associated generation of unacceptable electrical and acoustic noise, as well as the associated reduction in reliability. These electroosmotic pumps are preferably fabricated with materials and structures that improve performance, efficiency, and reduce weight and manufacturing cost relative to presently available micropumps. These electroosmotic pumps also preferably allow for recapture of evolved gases and deposited materials, which may provide for long-term closed-loop operation. Apparatus and methods according to the present invention also allow active regulation of the temperature of the device through electrical control of the flow through the pump and can utilize multiple cooling loops to allow independent regulation of the special and temporal characteristics of the device temperature profiles. Novel microchannel structures are also described.