62results about How to "Current can be suppressed" patented technology

A display device is disclosed. The display device includes: a pixel array part; and a drive part that drives the pixel array part. The pixel array part includes row-wise first scan lines and second scan lines, column-wise signal lines, pixels arranged in a matrix form on parts where the lines intersect, and power supply lines and ground lines that supply power to the respective pixels. The drive part includes a first scanner that sequentially supplies first control signals to the respective first scan lines and line-sequentially scans the pixels in units of rows, a second scanner that sequentially supplies second control signals to the respective second scan lines according to the line-sequential scan, and a signal selector that supplies video signals to the column-wise signal lines according to the line-sequential scan.

A solid-state imaging device includes a substrate, a photoelectric conversion element provided on the light incidence side of the substrate and including a photoelectric conversion film sandwiched between a first electrode provided separately for each of pixels, and a second electrode provided opposite the first electrode, the photoelectric conversion film being made of an organic material or an inorganic material and generating a signal charge according to the quantity of incident light, an amplifier transistor having an amplifier gate electrode connected to the first electrode, and a voltage control circuit that is connected to the second electrode, and supplies a desired voltage to the second electrode.

A back-illuminated type solid-state imaging device is provided in which an electric field to collect a signal charge (an electron, a hole and the like, for example) is reliably generated to reduce a crosstalk. The back-illuminated type solid-state imaging device includes a structure 34 having a semiconductor film 33 on a semiconductor substrate 31 through an insulation film 32, in which a photoelectric conversion element PD that constitutes a pixel is formed in the semiconductor substrate 31, at least part of transistors 15, 16, and 19 that constitute the pixel is formed in the semiconductor film 33, and a rear surface electrode 51 to which a voltage is applied is formed on the rear surface side of the semiconductor substrate 31.

A negative electrode 100 for a nonaqueous electrolytic secondary cell includes a current collector 1 and a plurality of active material bodies 2 formed on a surface of the current collector 1 at intervals; each active material body 2 contains a material for occluding or releasing lithium; and a plurality of projections 3 are formed on a part of a side surface of each active material body 2.

A car remote control system utilizing a signal in the form of electromagnetic wave or infrared ray called `keyless entry`. When receiving a predetermined wake-up signal, an MPU is once operated even when the received input signal is a noise signal to perform only judging operation of whether or not the input signal is normal. Only when judging that the input signal is a normal wake-up signal, the MPU controllably causes an electronic circuit to be shifted to a usual operation mode. When judging that the input signal is the noise signal prior to full input of the tuner signal, the MPU immediately shifts to a sleep mode. Thereby current consumption of an electronic control circuit can be suppressed.

At the starting time and an overload time in which the output voltage of the switching power source apparatus is low, if an overcurrent state, in which the ON period of the switching device becomes short and a current not less than the current limit value of the switching device flows through the switching device, occurs, this overcurrent state is detected. The blanking period of a blanking pulse signal is made shorter than the blanking period that is obtained during steady operation, and the ON period of the switching device is made shorter. Hence, the device current flowing through the switching device can be made small in each pulse for the switching operation, and, at the same time, the device current is suppressed from increasing each time a pulse for the switching operation is generated.

The invention relates to an apparatus(100) and a method for the processing of single molecules, particularly for the sensing or sequencing of single-stranded DNA. A bottom layer(110) and an electrically conductive top layer(120) with a first and a second slit(111,121), respectively, are disposed on top of each other such that an aperture(A) is formed by the slits. The slits(111,121) are preferably perpendicular to each other. An electrical circuit(140) may be connected to the top layer(120), allowing to sense single molecules that pass through the aperture(A).

In a manufacturing process of a display device, hydrogenation in an I layer of photodiodes D1 and D2 is progressed less than that in a channel portion of a pixel TFT, and a defect density due to dangling bonds not terminated in the I layer of the photodiodes D1 and D2 is made higher than a defect density in the channel portion of the pixel TFT. Thus, while suppressing a leakage current of the pixel TFT, the sensitivity of the photodiodes D1 and D2 to light is improved. Moreover, a gate electrode is provided above an i region of a pin-type optical sensor diode with an insulating film interposed therebetween. Thus, a gate voltage can control a threshold of a bias voltage when a current starts to flow into the optical sensor diode and a leakage current is prevented from flowing into the optical sensor diode.

An object of the present invention is to enable suppression of a leak current of an organic EL element while improving a conductivity of the organic EL element and suppressing an operation voltage thereof. An organic EL element is used which comprises at least a luminescent layer, a hole transport layer adjacent to a positive-electrode side of the luminescent layer, and an electron injection transport layer adjacent to a negative-electrode side of the luminescent layer, wherein a hole injection layer is provided between the hole transport layer and the positive electrode, and the conductivity of the hole injection layer continuously changes along a thickness direction of the hole injection layer.

A group III nitride semiconductor multilayer substrate (100) includes a channel layer (5) which is a group III nitride semiconductor, a barrier layer (6) which is formed on the channel layer (5) to form a heterointerface in combination with the channel layer (5) and which is a group III nitride semiconductor, wherein in the barrier layer (6, 206), a Cu concentration in a region of 10 nm or less depths from its surface is 1.0×1010 (atomicity / cm2) or less.

An object of the present invention is to improve the performance of a semiconductor device having a CMISFET. Each of an n channel MISFET and a p channel MISFET which form the CMISFET includes a gate insulating film composed of a silicon oxynitride film and a gate electrode including a silicon film positioned on the gate insulating film. Metal elements such as Hf are introduced near the interface between the gate electrode and the gate insulating film with a surface density of 1×1013 to 5×1014 atoms / cm2. The impurity concentration of channel regions of the n channel MISFET and the p channel MISFET is controlled to be equal to or lower than 1.2×1018 / cm3.

A semiconductor memory device comprises a memory cell array having a hierarchical word line structure including main word lines and sub-word lines; a main word driver for driving a non-selected main word line to high and for driving and activating a selected main word line to low; and a sub-word driver having a PMOS transistor whose gate is connected to the main word line for selectively activating the sub-word line corresponding to the selected main word line. The memory cell array is divided into a plurality of areas which is controlled such that a high level of each main word line is set to a first boost voltage in a predetermined area including the selected main word line, and a high level of each main word line is set to a second boost voltage lower than the first boost voltage in the other area.

A semiconductor integrated circuit device includes cells A-1, B-1, and C-1 that have the same logic. Cell B-1 has cell width W2 larger than a cell width of cell A-1, but gate length L1 of a MOS transistor is equal to that of cell A-1. Cell C-1 has cell width W2 equal to a cell width of cell B-1, but has a MOS transistor having large gate length L2. A circuit delay of cell C-1 becomes large as compared with that of cells A-1 and B-1, but leak current becomes small. Therefore, by replacing cell A-1 adjacent to a space area with cell B-1, and by replacing cell B-1 in a path having room in timing with cell C-1, for example, leak current can be suppressed without increasing a chip area.

Disclosed is a semiconductor laser light emitting device including: a stacked film composed of a stack of group III nitride semiconductor films each containing at least one kind selected from aluminum, gallium, indium, and boron; wherein an upper portion of the stacked film is formed into a ridge-like stripe, to form a current injection region; a current non-injection region formed on both sides of the ridge-like stripe; and at least part of the current non-injection region is made from a material expressed by a chemical formula AlxGa1-xN (0≦x≦1.0). In this device, the component ratio “x” of Al is specified at a value in a range of 0.3≦x≦1.0, so that the semiconductor laser light emitting device is configured as an index guide type semiconductor laser light emitting device; the component ratio “x” of Al is specified at a value in a range of 0.15<x<0.30, so that the semiconductor laser light emitting device is configured as a weak index type pulsation semiconductor laser light emitting device; or the component ratio “x” of Al is specified at a value in a range of 0≦x≦0.15, so that the semiconductor laser light emitting device is configured as a gain guide type laser light emitting device.

A selection circuit switches the output between a ancillary PWM signal NSPWM and a primary PWM signal SPWM in accordance with a power supply transition period or normal period. A ancillary signal generating circuit generates a gradually rising signal which is then amplified by a second driver circuit, so that a DC block capacitor is gradually charged and discharged. Thereby, the occurrence of noise due to an inrush current is prevented.

The object of the present invention is to increase the crystallization temperature of a hafnium compound film which can be effectively used as a high dielectric constant film of a gate oxide film of a MOSFET, for example. A hafnium silicate film is deposited on a substrate by reacting a vapor of a hafnium organic compound with a monosilane gas or a disilane gas in a reaction vessel in a heated vacuum atmosphere. Due to the crystallization restraining effect of silicon, the thus obtained film has a higher crystallization temperature. In another embodiment of the present invention, an oxygen-containing hafnium compound film is annealed in a heated ammonia gas atmosphere. The annealing also increase the crystallization temperature of the oxygen-containing hafnium compound film.

A PIN diode having improved avalanche resistance is provided. The PIN diode includes: a semiconductor substrate 11 that includes an N+ semiconductor layer 1, and an N− semiconductor layer 2; a P-type anode region 15 that is formed by selective impurity diffusion into an outer surface of the N− semiconductor layer 2; and an anode electrode 17 that is conducted to the anode region 15 through a contact region 17c in the anode region 15. The anode region 15 has a substantially rectangular outer edge of which four sides are adapted to be linear parts B2 and four vertices are adapted to be curved parts B1, and outside the contact region 17c, N-type non-diffusion corner regions 16 that extend along the curved parts B1 are respectively formed.

Disclosed herein is a display device including: a pixel array part configured to include scan lines disposed along rows, signal lines disposed along columns, and pixels that are disposed at intersections of the scan lines and the signal lines and are arranged in a matrix; and a drive part configured to have at least a write scanner that sequentially supplies a control signal to the scan lines to thereby carry out line-sequential scanning and a signal selector that supplies a video signal to the signal lines in matching with the line-sequential scanning.

To save power consumption in a semiconductor integrated circuit 2A increased due to a leak current caused by a variation in a manufacturing process, temperature, and a power supply voltage. A semiconductor integrated circuit 2A, a leak current detection circuit 3, a comparison operation circuit 4 and an applied voltage output circuit 5A are provided. The semiconductor integrated circuit 2A has a circuit body 21 including a plurality of functional MOSFETs for performing predetermined functional operations, and a monitor circuit 22A including a plurality of monitor NMOSFETs 23 for monitoring properties of the functional MOSFETs. The leak current detection circuit 3 detects leak data corresponding to leak currents from the monitor NMOSFETs 23, and outputs the detected leak data. The comparison operation circuit 4 extracts, from a plurality of pieces of leak data, one piece of leak data minimizing a leak current in the circuit body 21, and outputs the extracted leak data as applied voltage data. The applied voltage output circuit 5A sets and outputs a source-drain voltage to be applied to the functional MOSFETs based on the applied voltage data.

Provided is a coupling structure for airframe components that is capable of ensuring sufficient lightning protection capability. A conductive pattern part 40 made of a conductive material is formed around each fastener member 24 between wing surface panels 21A and 21B. The conductive pattern part 40 is formed, for example, around each of holes 21c and 21d on the plane on which the wing surface panel 21A and the wing surface panel 21B abut against each other. Then, the conductive pattern part 40 is pushed against both the wing surface panel 21A and the wing surface panel 21B by the fastening power of the fastener members 24, whereby electrical conduction between the wing surface panel 21A and the wing surface panel 21B can be achieved.

A motor control device for controlling a brushless DC motor in a PWM control manner using an inverter circuit according to a position-sensorless method includes: a ripple current estimating device; and a control device. When the magnitude of the ripple current is less than or equal to a threshold value, the control device performs balanced-drive switching that a first output terminal of the inverter circuit is repeatedly and alternately connected to high and low voltage sides of a drive power supply, and the second output terminal of the inverter circuit is repeatedly and alternately connected to the low and high voltage sides. When the magnitude of the ripple current exceeds the threshold value, the control device performs unbalanced-drive switching that the first output terminal is repeatedly and alternately connected to the high and low voltage sides, and the second output terminal is connected only to the low voltage side.

In a manufacturing process of a display device, hydrogenation in an I layer of photodiodes D1 and D2 is progressed less than that in a channel portion of a pixel TFT, and a defect density due to dangling bonds not terminated in the I layer of the photodiodes D1 and D2 is made higher than a defect density in the channel portion of the pixel TFT. Thus, while suppressing a leakage current of the pixel TFT, the sensitivity of the photodiodes D1 and D2 to light is improved. Moreover, a gate electrode is provided above an i region of a pin-type optical sensor diode with an insulating film interposed therebetween. Thus, a gate voltage can control a threshold of a bias voltage when a current starts to flow into the optical sensor diode and a leakage current is prevented from flowing into the optical sensor diode.

A semiconductor memory device comprises a memory cell array having a hierarchical word line structure including main word lines and sub-word lines; a main word driver for driving a non-selected main word line to high and for driving and activating a selected main word line to low; and a sub-word driver having a PMOS transistor whose gate is connected to the main word line for selectively activating the sub-word line corresponding to the selected main word line. The memory cell array is divided into a plurality of areas which is controlled such that a high level of each main word line is set to a first boost voltage in a predetermined area including the selected main word line, and a high level of each main word line is set to a second boost voltage lower than the first boost voltage in the other area.

Provided is an internal power supply voltage generation circuit, with which a through current can be prevented from being excessive due to manufacturing fluctuations during the operation of a logic circuit, to thereby suppress current consumption. Provided is an internal power supply voltage generation circuit for generating an internal power supply voltage at an internal power supply terminal and supplying the internal power supply voltage to a logic circuit, the internal power supply voltage generation circuit including: a transistor having a source follower configuration for outputting a voltage applied to a gate thereof; and a current limiting circuit for limiting a maximum current of the transistor having the source follower configuration for outputting the voltage applied to the gate thereof, to thereby suppress a maximum current supplied to the logic circuit and suppress current consumption.

A semiconductor storage apparatus provides a large capacity phase-change memory possessing high speed operation, low electrical current, and high-reliability. During the period that a read-out start signal is activated in the memory region control circuit and the block of pairs of sense-latch and write driver is performing the verify read in the upper section memory region; the write enable signals in the memory region control circuit are activated and the block of pairs of sense-latch and write driver perform rewrite operation of the data in the lower section memory region. This type of operation allows cancelling out the time required for the verify read and the time required for the time-division write operation by performing the verify read in one memory region, while performing time-division rewrite in other memory region, to achieve both higher reliability rewrite operation along with suppressing the rewrite operation peak electrical current.

At the starting time and an overload time in which the output voltage of the switching power source apparatus is low, if an overcurrent state, in which the ON period of the switching device becomes short and a current not less than the current limit value of the switching device flows through the switching device, occurs, this overcurrent state is detected. The blanking period of a blanking pulse signal is made shorter than the blanking period that is obtained during steady operation, and the ON period of the switching device is made shorter. Hence, the device current flowing through the switching device can be made small in each pulse for the switching operation, and, at the same time, the device current is suppressed from increasing each time a pulse for the switching operation is generated.

Semiconductor structures and fabrication methods are provided. An exemplary fabrication method includes providing a semiconductor substrate having a fin material layer on the semiconductor substrate; forming an isolation material layer having a bandgap greater than a bandgap of the fin material layer on the fin material layer; and forming a stacked channel material layer on the isolation material layer. The stacked channel material layer includes a sacrificial material layer and a channel material layer on the sacrificial material layer. The method also includes etching the stacked channel material layer, the isolation material layer and the fin material layer to form fins protruding from the semiconductor substrate, an isolation layer on the fins and a stacked channel layer on the isolation layer. The stacked channel layer includes a sacrificial layer and a channel layer on the sacrificial material layer.