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52results about How to "Reduced carrier mobility" patented technology

Multiple-plane finFET CMOS

The present invention provides FinFETs on the same substrate utilizing various crystal planes for FET current channels in order to optimize mobility and / or to reduce mobility. An embodiment of the present invention provides a substrate having a surface oriented on a first crystal plane that enables subsequent crystal planes for channels to be utilized. A first transistor is also provided having a first fin body. The first fin body has a sidewall forming a first channel, the sidewall oriented on a second crystal plane to provide a first carrier mobility. A second transistor is also provided having a second fin body. The second fin body has a sidewall forming a second channel, the sidewall oriented on a third crystal plane to provide a second carrier mobility that is different from the first carrier mobility.
Owner:GLOBALFOUNDRIES US INC

Ferro-electric field effect transistor based on structured carbon nano tube striped array and manufacturing method thereof

The invention discloses a ferro-electric field effect transistor based on a structured carbon nano tube striped array and a manufacturing method of the ferro-electric field effect transistor. According to the unit structure of the transistor, a bottom electrode layer (1) is arranged on the bottom layer, a ferro-electric film insulated gate layer (2) and a structured carbon nano tube striped array channel layer (3) are sequentially arranged on the middle layer, and a top layer is arranged on the structured carbon nano tube striped array channel layer (3) and comprises a transistor source electrode (4) and a transistor drain electrode (5); carbon nano tubes are single-walled carbon nano tubes, or double-walled carbon nano tubes or multi-walled carbon nano tubes. According to the ferro-electric field effect transistor, the on-state current and the switch ratio are large, carrier mobility is high, the starting voltage is small, the storage window is wide, and meanwhile the ferro-electric field effect transistor has the advantages of being simple in structure and a buffering layer is not needed, interface contact between a ferro-electric layer and a semiconductor layer is good, and large-area soft devices are easy to obtain. The manufacturing method is simple in technology, convenient to operate and low in cost and dispense with expensive equipment, and large-area and large-scale industrial production is easy to realize.
Owner:XIANGTAN UNIV

Semiconductor device and its fabrication method

A semiconductor device includes a first MIS transistor, and a second MIS transistor having a threshold voltage higher than that of the first MIS transistor. The first MIS transistor includes a first gate insulating film made of a high-k insulating film formed on a first channel region, and a first gate electrode having a first conductive portion provided on and contacting the first gate insulating film and a second conductive portion. The second MIS transistor includes a second gate insulating film made of the high-k insulating film formed on a second channel region, and a second gate electrode having a third conductive portion provided on and contacting the second gate insulating film and a fourth conductive portion. The third conductive portion has a film thickness smaller than that of the first conductive portion, and is made of the same composition material as that of the first conductive portion.
Owner:PANNOVA SEMIC

Method for improving write redundancy of high SRAM (static random access memory)

The invention discloses a method for improving write redundancy of a high SRAM (static random access memory). An NMOS (n-channel metal oxide semiconductor), a PMOS (p-channel metal oxide semiconductor) and an upper pulling pipe with cover layers are involved. The method comprises the following steps of: firstly simultaneously removing the cover layers of the NMOS device and the upper pulling pipe; and carrying out carbon injection on the PMOS and the upper pulling pipe with the cover layers so that a source drain end of the NMOS and a source drain end of the upper pull pipe form a crystal lattice structure and the tensile stress in a channel direction is improved. Through the method for improving the write redundancy of the high SRAM, disclosed by the invention, a carbon injection process is utilized to the source drain end of the upper pull pipe so that the tensile stress of the upper pull pipe in the channel direction is improved, the carrier mobility of the upper pull pipe is effectively reduced, the equivalent resistance of the upper pull pipe is increased, and simultaneously the write redundancy of an RAM (random-access memory) is improved.
Owner:SHANGHAI HUALI MICROELECTRONICS CORP
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