36results about How to "Reduce EOT" patented technology

Thin effective gate oxide thickness with reduced leakage for replacement metal gate transistors is achieved by forming a protective layer between the gate oxide layer and metal gate electrode, thereby reducing stress. Embodiments include forming a protective layer of amorphous carbon containing metal carbides decreasing in concentration from the metal gate electrode toward the gate oxide layer across the protective layer. Embodiments of methodology include removing the removable gate, depositing a layer of amorphous carbon on the gate oxide layer, forming the metal gate electrode and then heating at an elevated temperature to diffuse metal from the metal gate electrode into the amorphous carbon layer, thereby forming the metal carbides. Embodiments also include metal gate transistors with a gate oxide layer having a high dielectric constant and silicon concentrated at the interfaces with the metal gate electrode and substrate.

The metal gate structure of the present invention can include a TiN complex, and the N / Ti proportion of the TiN complex is decreased from bottom to top. In one embodiment, the TiN complex can include a single TiN layer, which has an N / Ti proportion gradually decreasing from bottom to top. In another embodiment, the TiN complex can include a plurality of TiN layers stacking together. In such a case, the lowest TiN layer has a higher N / Ti proportion than the adjusted TiN layer.

In a MIS transistor of which gate length is 10 nm or less, a gate insulator comprising a silicon oxide film formed on a silicon substrate and a high-k film formed on the silicon oxide film has a nitrided region including more nitrogen at the lateral side than at the central side in the gate-length direction, and including more nitrogen at the upper side than at the lower side in the film thickness direction. The reliability and characteristics of a MIS transistor using a gate insulator including a high-k (high dielectric constant) film is enhanced.

In a MIS transistor of which gate length is 10 nm or less, a gate insulator comprising a silicon oxide film formed on a silicon substrate and a high-k film formed on the silicon oxide film has a nitrided region including more nitrogen at the lateral side than at the central side in the gate-length direction, and including more nitrogen at the upper side than at the lower side in the film thickness direction. The reliability and characteristics of a MIS transistor using a gate insulator including a high-k (high dielectric constant) film is enhanced.

A method for forming a MIM capacitor structure includes the steps of obtaining a base structure provided with a recess, the recess exposing a conductive bottom electrode plug; selectively growing Ru on the bottom electrode plug, based on a difference in incubation time of Ru growth on the bottom electrode plug compared to the base structure material; oxidizing the selectively grown Ru; depositing a Ru-comprising bottom electrode over the oxidized Ru; forming a dielectric layer on the Ru-comprising bottom electrode; and—forming a conductive top electrode over the dielectric layer.

The invention relates to the field of semiconductor manufacturing and provides a method for manufacturing a semiconductor device. The method comprises the following steps: providing a semiconductor substrate; forming an interface layer, a gate dielectric layer and a metal work function layer on the substrate; forming a diffusion barrier layer on the metal work function layer; forming a metal oxygen absorbing layer on the diffusion barrier layer; and carrying out thermal annealing treatment on the device so as to ensure the metal oxygen absorbing layer to absorb the oxygen in the interface layer to reduce the thickness of the interface layer and ensure the diffusion barrier layer to prevent the oxygen absorbing metals in the metal oxygen absorbing layer from being diffused into the metal work function layer. By adopting the method, the oxygen absorbing metals can be prevented from being diffused into the work function layer and / or gate dielectric layer while the thickness of the interface layer is reduced, thus reducing the equivalent oxide thickness under the premise of not affecting the threshold voltage of the device.

The invention discloses a semiconductor device manufacturing method, comprising: forming a gate stack structure on a substrate; sequentially depositing a first dielectric material layer and a second dielectric material layer on the substrate and the gate stack structure; using helium-containing The etching gas sequentially etches the second dielectric material layer and the first dielectric material layer to form the second sidewall and the first sidewall respectively. According to the semiconductor device manufacturing method of the present invention, the double-layer composite sidewall and the etching gas containing helium are used for two-step etching, which reduces the damage to the substrate and also reduces the complexity of the process. In addition, the valve can be optimized. Value voltage, effectively reduce EoT, improve gate control capability and drive current.

The present invention provides a method for preparing a semiconductor device and the prepared semiconductor device. The method includes: providing a semiconductor substrate; forming a rear gate groove on the semiconductor substrate; forming an interface oxide layer on the rear gate groove; A high-k gate dielectric layer is formed on the interface oxide layer; a diffusion barrier layer is formed on the high-k gate dielectric layer; a functional metal layer is formed on the diffusion barrier layer, wherein the functional metal layer can reduce the equivalent oxide layer thickness; the functional metal layer The upper square success function metal layer; forming a metal filling layer to fill the rear gate groove. According to the method for reducing EOT provided by the present invention, that is, in the gate stack, using a metal layer with the function of reducing the equivalent oxide thickness (EOT) can reduce the EOT of the gate stack structure, and provide a solution for improving the performance of small-sized devices .