Method for manufacturing semiconductor device

Abstract

The invention relates to the field of semiconductor manufacturing and provides a method for manufacturing a semiconductor device. The method comprises the following steps: providing a semiconductor substrate; forming an interface layer, a gate dielectric layer and a metal work function layer on the substrate; forming a diffusion barrier layer on the metal work function layer; forming a metal oxygen absorbing layer on the diffusion barrier layer; and carrying out thermal annealing treatment on the device so as to ensure the metal oxygen absorbing layer to absorb the oxygen in the interface layer to reduce the thickness of the interface layer and ensure the diffusion barrier layer to prevent the oxygen absorbing metals in the metal oxygen absorbing layer from being diffused into the metal work function layer. By adopting the method, the oxygen absorbing metals can be prevented from being diffused into the work function layer and / or gate dielectric layer while the thickness of the interface layer is reduced, thus reducing the equivalent oxide thickness under the premise of not affecting the threshold voltage of the device.

Description

technical field [0001] The present invention generally relates to a manufacturing method of a semiconductor device, and in particular, relates to a threshold voltage control method of a gate region of a CMOS device. Background technique [0002] For decades in the development of microelectronics technology, logic chip manufacturers have been using SiO2 when manufacturing MOS devices. 2 As the gate dielectric, heavily doped polysilicon is used as the gate electrode material. However, as feature sizes continue to shrink, SiO in MOS transistors 2 The gate dielectric is approaching its limit. For example, in a 65nm process, SiO 2 The thickness of the gate dielectric has been reduced to 1.2 nanometers, which is about 5 silicon atomic layers thick. If it continues to shrink, the leakage current and power consumption will increase sharply. At the same time, problems such as the diffusion of doped boron atoms caused by the polysilicon gate electrode, the polysilicon depletion ef...

AI Technical Summary

Problems solved by technology

However, in high-k / metal gate processes, the interfacial layer becomes thicker during the annealing process due to the necessary annealing process

However, due to the very serious short-channel effect in CMOS devices below 45nm, a gate dielectric with an EOT (Equivalent Oxide Thickness) of no more than 1nm is required to improve the control ability of the channel, so a thick interface layer SiO 2 is unacceptable

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