Patents
Literature
Hiro is an intelligent assistant for R&D personnel, combined with Patent DNA, to facilitate innovative research.
Hiro

131results about How to "Upper surface" patented technology

Method for manufacturing semiconductor device

In a conventional method for manufacturing a semiconductor device, there are problems that a concave part is formed in a formation region of an isolation region, no flat surface is formed in the isolation region, and a wiring layer is disconnected above the concave part. In a method for manufacturing a semiconductor device of the present invention, when a silicon oxide film used for a STI method is removed, an HTO film covering an inner wall of a trench is partially removed to form a concave part in an isolation region. Thereafter, a TEOS film is deposited on an epitaxial layer including the concave part and is etched back. Accordingly, an insulating spacer is buried in the concave part. Thus, an upper surface of the isolation region becomes a substantially flat surface. Consequently, even if a wiring layer is formed above the concave part in the isolation region, disconnection thereof can be prevented. Moreover, in the isolation region, the substantially flat surface makes it possible to form a passive element such as a capacity element.
Owner:SEMICON COMPONENTS IND LLC

Multi-axial machine tool and table unit mounting jig

In the multi-axial machine tool, a table unit is detachably mounted on the upper surface of the interior portion of a portal bed disposed on a leg. The table unit comprises a table base fixed to the upper surface of the leg, a turning table which, when it is viewed at a reference working position, is turnably disposed on an inclined turning surface of the table base formed so as to be inclined in a descending manner toward a front side of the machine tool, and a work table disposed on the table support portion of the turning table so as to be turnable around axes lying in parallel with the axis of a spindle.
Owner:DMG MORI SEIKI CO LTD

Nonvolatile semiconductor storage device

In a nonvolatile semiconductor storage device having a plurality of NAND strings, each NAND string includes a memory cell block obtained by connecting a plurality of nonvolatile memory cells in series, a first selection gate transistor connected to a data transfer line contact, and a second selection gate transistor connected to a source line contact. The upper surface of an isolation insulating film between adjacent data transfer line contacts is higher than the major surface of a semiconductor substrate in a device area between the first selection gate transistor and data transfer line contact. Alternatively, the upper surface of an isolation insulating film between adjacent source line contacts is higher than the major surface of the semiconductor substrate in a device area between the second selection gate transistor and source line contact.
Owner:KK TOSHIBA
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products