Anti-fuse memory cell

Abstract

An anti-fuse memory cell having a variable thickness gate oxide. The variable thickness gate oxide is formed by depositing a first oxide over a channel region of the anti-fuse memory cell, removing the first oxide in a thin oxide area of the channel region, and then thermally growing a second oxide in the thin oxide area. The remaining first oxide defines a thick oxide area of the channel region. The second oxide growth occurs under the remaining first oxide, but at a rate less than thermal oxide growth in the thin oxide area. This results in a combined thickness of the first oxide and the second oxide in the thick oxide area being greater than second oxide in the thin oxide area.

Description

technical field [0001] The present invention generally relates to non-volatile memory. More specifically, the present invention relates to antifuse memory cell structures. Background technique [0002] Over the past 30 years, antifuse technology has attracted a great deal of attention from inventors, integrated circuit designers and manufacturers. An antifuse is a structure that can change to a conducting state, or in other words, an electronic device that changes from a non-conducting to a conducting state. Equivalently, the binary state can be one of high and low resistance in response to electrical stress, such as a programming voltage or current. There have been many attempts to develop and apply antifuses in the microelectronics industry, but the most successful applications of antifuses to date can be seen in Field Programmable Gate Array (FGPA) devices made by Actel and Quicklogic, and in DRAM devices by Micron. Redundancy or option programming used in access memor...

AI Technical Summary

Problems solved by technology

[0020] Although Peng implemented a cross-point memory structure, his array required CMOS process modifications (LDD elimination, thicker gate oxide at the edges) and had the following disadvantages: (a) all row decoders, column decoders Detectors and sense amplifiers must switch over a wide voltage range of 8V / 3.3V / 0V or 8V / 1.8V / 0V

[0024] All prior art antifuse cells and arrays either require special processing steps or have issues with high voltage exposure of the MOS switching elements, causing manufacturability and reliability issues

They are also limited to low-density memory applications (except for Peng's single-transistor cells), which in turn has very questionable manufacturability

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