45 results about "Solar transition region" patented technology

Methods of forming power semiconductor devices include forming a semiconductor substrate having a drift region of first conductivity type therein and a transition region of first conductivity type that extends between the drift region and a first surface of the semiconductor substrate. A gate electrode is formed on the first surface. Base and base shielding region dopants are implanted into the transition region using the gate electrode as an implant mask. A plurality of annealing steps are performed so that the base shielding region dopants are driven in laterally and vertically to substantially their full and final depth within the substrate and thereby define first and second base shielding regions that constrict a neck of the transition region to a minimum width.

The invention provides a surface nanotechnology locally-processed thin-wall energy absorption tube, and belongs to the technical field of automobile collision. The surface nanotechnology locally-processed thin-wall energy absorption tube is characterized in that surface local nanotechnology processing is performed on the structure of the thin-wall energy absorption tube, the design of interval strip-shaped or interval sheet-shaped nanocrystallization areas locally distributed in the axial direction and the annular direction and a layout design are adopted in the surface local nanotechnology processing, and a single local nanocrystallization surface shape design and a nanocrystallization degree design are further adopted in the surface local nanotechnology processing. The thin-wall energy absorption tube is divided into one to three sections and a transition section, and different surface nanocrystallization layout designs are adopted in the sections. The surface nanotechnology locally-processed thin-wall energy absorption tube has the advantages that through surface nanometer local process of the thin-wall energy absorption tube, a specific buckling mode and a specific development path of the thin-wall tube are induced, the effect that energy absorption is conducted at different sections when impact occurs is achieved, and the energy absorption effect of the thin-wall tube is improved. According to the design method of the thin-wall energy absorption tube, the structure of the energy absorption tube and the process of the energy absorption tube are made to be simple, the appearance of an original thin-wall tube is kept, and the thin-wall energy absorption tube further has the advantages of stability and controllability, and can be applied to automobile energy absorption structures, anti-collision safety equipment and other carrying vehicle energy absorption devices.

An interconnect structure which includes a plating seed layer that has enhanced conductive material, preferably, Cu, diffusion properties is provided that eliminates the need for utilizing separate diffusion and seed layers. Specifically, the present invention provides an oxygen / nitrogen transition region within a plating seed layer for interconnect metal diffusion enhancement. The plating seed layer may include Ru, Ir or alloys thereof, and the interconnect conductive material may include Cu, Al, AlCu, W, Ag, Au and the like. Preferably, the interconnect conductive material is Cu or AlCu. In more specific terms, the present invention provides a single seeding layer which includes an oxygen / nitrogen transition region sandwiched between top and bottom seed regions. The presence of the oxygen / nitrogen transition region within the plating seed layer dramatically enhances the diffusion barrier resistance of the plating seed.

The invention discloses a control method for an external extension transition section on a heavy doping arsenic underlay, which adopts chemical vapor deposition technology to grow light doping thin silicon extension layer at two times on a n-type heavy doping arsenic silicon underlay. After the growing of a first own extension layer, reduce the temperature to 870 to 930 DEG C. and take it out. During the process, remove the memory effect by putting in a HCI erosion base. After the completion of erosion, place the piece in furnace under the temperature of 870 to 930 DEG C. and then grow the residual extension layer. By checking and comparing the extension layer made with ordinary method and the method in the invention via an extension resistance analyzer, it is proved that the extension layer made of the method in the invention has steepy transition section and resistance of the extension layer has excellent evenness.

The present invention relates to a novel infrared detector BIB silicon epitaxial wafer manufacturing method. An N-type (100) polished wafer with heavily doped As, the electrical resistivity is <=0.004[Omega].cm, and there is not a back-seal substrate. In order to reduce the back-face self doping influence, a silicon package process is adapted. Surface impurities and defects are removed through HCI in-situ high-temperature polishing so as to improve the substrate surface quality. Substrate self-doping is reduced through a high-flow high-temperature blowdown process. a two-step extrapolation isemploys to allow a low-resistance absorption layer and an intrinsic layer to be separately grown, and high-flow H2 cooling blowdown between the two steps; and a cavity is subjected to high-flow gas corrosion prior to wafer installation of the epitaxy of the intrinsic layer, the low-speed and low-temperature growth is performed when epitaxy is performed. The novel infrared detector BIB silicon epitaxial wafer manufacturing method controls self-doping, a transition area of the absorption layer and the substrate is steep, the intrinsic barrier layer has a wide flat area so as to meet the demandof the BIB device design.

A superjunction device is disclosed. A protective epoxidation film surrounding the periphery of the charge flow region is provided, the aspect ratio of the contact hole in the transition region is greater than or equal to the aspect ratio of the contact hole in the charge flow region, and the tungsten plug process is used to fill the contact holes with different aspect ratios reliably at the sametime. The width of the P-type well is smaller than the width of the P-type column, and a slowly varying junction diode is formed between the P-type well and the N-type region. The invention also discloses a manufacturing method of a superjunction device. The invention can reliably fill the contact hole in the transition region when the height-to-width ratio is high, at that same time, the anti-avalanche breakdown ability of the device is not affect by the contact hole process of the transition region, and the influence of the P-type well on the width of the N-type region at the position of thechannel region is reduce, so that the on resistance of the device is reduced; and the nonlinearity of the output capacitance of the device is improved and the EMI problem in device application is improved.