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Control method for extension slice equability for 6 inch As back lining MOS part

A technology of MOS device and control method, which is applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve the problems of unsatisfactory self-doping, unsatisfactory edge uniformity, unfavorable mass production, etc. time, the effect of reducing process time and reducing production costs

Active Publication Date: 2008-02-13
HEBEI POSHING ELECTRONICS TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The time of this method of gas removal is the method that has been used all the time. The time of gas removal is the same for two times. This not only wastes a lot of time, but also the control of self-doping is not very ideal, which is extremely unfavorable for mass production.
6-inch self-doping is more serious than 4-inch, and the control of edge uniformity is far from ideal

Method used

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  • Control method for extension slice equability for 6 inch As back lining MOS part

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Experimental program
Comparison scheme
Effect test

Embodiment 1

[0037] 1. Substrate requirements: the following table.

[0038]

Parameter

Unit (unit)

specification

value

(standard value)

Dopant

Arsenic / arsenic

Resistivity (resistivity)

CM

0.002-0.004

RRG MAX

(resistivity radial gradient position)

％

25.0

Orientation

Degree (degree)

1-1-1

Off Orientation

(Deviation of crystal orientation)

Degree (degree)

4.0°±0.5°

Thickness and thickness

tolerance

(thickness and tolerance)

Microns (microns)

6260±20.0

Diameter and diametrical

tolerance

(diameter and tolerance)

mm (mm)

150.0+0.20

Back side

A

5000±500

[0039] 2. Extension parameters

[0040] The resistivity of the epitaxial layer is 24±8%Ω·cm, and the thickness of the epitaxial layer is 50±5%μm.

[0041] 3. The epitaxial equipmen...

Embodiment 2

[0051] The difference between this embodiment and the embodiment is that: the first time in the process 4.2 with large flow H 2 The flushing time is 30 minutes; the second time in 4.5 with large flow of H 2 Rinse and catch air for 5 minutes.

Embodiment 3

[0053] The difference between this embodiment and the embodiment is that: the first time in the process 4.2 with large flow H 2 The flushing time is 25 minutes; the second time in 4.5 with large flow of H 2 In the middle of the wash, the time is 7 minutes.

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Abstract

The present invention discloses a 6 inch As dorsal closure substrate MOS device epitaxial slice uniformity controlling method. The processing steps of the method are: HCL in-situ polishing--first high-flow H2 drive gas--temperature reduction--growth of intrinsic layer--the second high-flow H2 drive gas--the process of growth of epitaxial layer of remaining thick. The time for the first high-flow H2 drive gas is 20 to 30 minutes, the time for the second high-flow H2 drive gas is 5 to 10 minutes. After repeat tests, the optimal drive gas time of the present invention is capable of controlling self-doping, increasing epitaxial slice electrical resistivity edge uniformity. The spreading resistance flatness and the transition zone abruptness of the epitaxial slice produced by the present invention are better than those of epitaxial slice produced by traditional method.

Description

technical field [0001] The invention relates to a production method of MOS device epitaxial wafers, in particular to a method for controlling the uniformity of MOS device epitaxial wafers with a 6-inch As backsealing substrate. Background technique [0002] Silicon epitaxial wafer is the main material for making semiconductor discrete devices, because it can not only ensure the high breakdown voltage of PN junction, but also reduce the forward voltage drop of the device. At the same time, silicon epitaxial wafer is the main material of bipolar integrated circuit (IC). Manufacturing process, it can not only make IC devices on the lightly doped epitaxial layer with heavily doped buried layer, but also form a grown PN junction, which solves the isolation problem of IC. Making CMOS circuits with silicon epitaxial wafers can suppress latch-up (Latchup) effect and resist soft errors generated by alpha particles, so silicon epitaxial wafers are increasingly used in CMOS devices. I...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/02H01L21/20
Inventor 薛宏伟
Owner HEBEI POSHING ELECTRONICS TECH
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