101results about How to "Add process steps" patented technology

The invention belongs to the technique area of the semiconductor elements and devices. Three layers of the isolation pole are prepared on the graphics of the first electrode. The graphics of the first layer of the isolation pole is the mesh texture with the cross section being as trapezoid shape. The cross section of the lines on the second layer and the third layer of the isolation pole possess the shape with big at the upper and small at the lower. Then, the organic function layer and the second electrode are deposited in sequence. The shadow effect caused by the shape with big at the upper of the second layer and the third layer makes the second electrode possible to be partitioned. The first layer of the isolation pole being equivalent to 'insulating base' prevents the short circuit between the electrodes.

The invention discloses a lithium NCM (nickel cobalt manganese) material. The lithium NCM material is prepared by doping Mg (magnesium), Al (aluminum) or Ti (titanium) and F (fluorine) into a 811 type lithium NCM cathode material. The lithium nickel manganese cobalt material has the advantages that by simultaneously doping Mg, Al or Ti and F into the 811 type NCM electrode material, the rate discharge property and specific capacity of the material are effectively improved; the corrosion of HF (hydrogen fluoride) to the material is effectively inhibited, the dissolving of Co is reduced, and the structure stability and thermal stability of the material are greatly improved.

The invention discloses a sheet bonding method in a substrate thinning technique, which comprises the following steps: coating an electron beam photoresist on the front surface of a substrate; coating a PMGI layer on the electron beam photoresist; bonding the front surface of the substrate onto a thinning sheet support by using high temperature wax; bonding the thinning sheet support onto a thinning glass sheet by using low temperature wax; carrying out thinning technique on the back surface of the substrate; removing the low temperature wax, and taking the thinning sheet support with the substrate off the thinning glass sheet; and completing subsequent photoresist removal after other back surface techniques, and separating the substrate from the thinning sheet support. The method effectively solves the problem of mutual solubility between the photoresist and high temperature wax, and enhances the technical efficiency and technical yield of the thinning technique.

The invention discloses a method for recycling valuable metal in a waste circuit board. The method includes the following steps that the waste circuit board is subject to smashing and reselection to prepare multi-metal powder; a dilute acid solution is added into the multi-metal powder, agitation leaching is carried out, filtering is carried out, and leaching slag I and leaching liquid I are obtained; an acid solution is added into the leaching slag I according to the liquid-solid mass ratio of the acid solution to the leaching slag I being 10-40:1, then an oxidizing agent is added, agitation leaching is carried out, filtering is carried out after leaching is finished, and leaching slag II and leaching liquid II are obtained; the leaching liquid II is subject to cyclone electrodeposition to obtain cathode copper and an after-electrolysis solution; alkali and a reducing agent are added into the leaching slag II, smelting is carried out under the condition that the temperature ranges from 400 DEG C to 600 DEG C, water leaching is carried out, filtering is carried out, and lead bullion containing precious metal and leaching liquid III are obtained; and the leaching liquid III is purified and is subject to evaporation and concentration to obtain a concentrated alkali solution and sodium stannate crystals. According to the method for recycling the valuable metal in the waste circuit board, the procedure is short, the efficiency is high, the cost is low, cleanness is achieved, and pollution is avoided.

The invention provides a TFT-LCD (thin film transistor-liquid crystal display) array panel structure and a production method thereof. An anti-ESD (anti-electrostatic discharge) element of which a gate metal layer is in direct contact with a source/drain metal layer is produced outside a TFT array in order to prevent each process station after source/drain metal deposition from being injured by static electricity, so that the product percent of pass can be increased; meanwhile, by correspondingly changing active mask, silicon islands are formed in the process of via-hole mask, consequently, the process steps are simplified, and the production cost is reduced; meanwhile, by correspondingly changing gate mask, active mask and source/drain mask, the gate metal is covered by the source/drain metal in the area of a VT/FPC/IC pad, consequently, the electrode corrosion of the gate metal layer can be reduced, and in the extending area of a fanout line, the line resistance can be decreased; and furthermore, before the deposition of the gate metal layer, a silicon nitride layer is first formed, so that the injuries of a substrate caused by dry etch can be reduced.

Disclosed are a resistance change memory device, a method of fabricating the same, and a resistance change memory array including the same. The resistance change memory device includes a first electrode and a second electrode. A hybrid switching layer is interposed between the first electrode and the second electrode. The hybrid switching layer is a metal oxide layer having both threshold switching characteristics and memory switching characteristics.

The invention provides an electrically erasable programmable read-only memory (EEPROM) core structure formed by a process embedded into a monolithic integration process of manufacturing a bipolar transistor, a complementary metal oxide semiconductor (CMOS) device and a double-diffusion metal oxide semiconductor (DMOS) device on an identical chip (BCD) and a forming method. The EEPROM core structure formed by the process embedded into the BCD process comprises a selectron and a memotron which are connected in series, wherein the selectron is a laterally diffused n-CHANNEL metal oxide semiconductor (LDNMOS) transistor. In the invention, the forming process of the EEPROM core structure can be embedded into the BCD process to achieve favorability for reducing the complexity of the process.

The invention relates to a grounding shield structure which applies a fractal theory. In existing on-chip spiral inductors and transformers, because an alternating electromagnetic field is produced, induction current is produced on a substrate, energy loss is produced, and an induction value and a Q value are reduced. The shield structure is arranged in the center of an inductor/transformer which is wound from a coil, and a pattern grounding shield layer of a first order, a second order, a third order and even a higher order is constructed with metal layers M1 and M2 with thin bottom layers based on H-shaped and crisscross basic units through the self similarity and iterative principle of the fractal theory. According to the novel fractal pattern grounding shield structure, the electromagnetic field which penetrates to the substrate is effectively shielded, so that the induction current which can be produced on the substrate and on the surface area of the substrate is reduced, and the effects of reducing the energy loss of the substrate and improving the induction value and a quality factor are achieved.

The invention discloses a production method of bromo-3-chloro-5,5-dimethylhydantoin (BCDMH) serving as a chemical intermediate. The production method comprises the following steps that A, 5,5-dimethylhydantoin, flake caustic soda, liquid bromine and chlorine react; a reaction material is obtained; B, the reaction material is subjected to centrifugal spin-drying by a scraper bottom unloading centrifuge, subjected to centrifugal washing by deionized water, and spin-dried; a wet product after centrifugal treatment is dried to form a dry product; and C, the dry product is dissolved by acetone, and filtered; after the deionized water is added for diluting and cooling, BCDMH is separated through crystallization; and the dried wet product is BCDMH capable of serving as a chemical oxidizing agent. The content of BCDMH prepared by the method reaches above 99.3%; the content of bromine is 32.85%; the content of chlorine is 14.70%; a trichloromethane insoluble substance is less than or equal to 0.03%; iron ions are less than or equal to 8mg/kg; calcium ions are less than or equal to 24mg/kg; and BCDMH can serve as the chemical intermediate.

A chlorination method for industrial production of sucralose-6-acetate. The method comprises steps of: (a) adding thionyl chloride into an organic solvent below 30 DEG C to form a mixed solution, with a molar ratio of the organic solvent to thionyl chloride of 3.5-4.6:1; (b) adding sucrose-6-acetate with water content of 0.2%-0.8% into the mixed solution, and stirring, wherein a molar ratio of added sucrose-6-acetate to thionyl chloride is 1:7-9; and (c) slowly heating to 110-113 DEG C in 6-7 h; and after the reaction, subjecting the reaction product to neutralization, solvent removal, decolorization by adding water and crystallization to obtain the sucralose-6-acetate crude product. According to the invention, sucrose-6-acetate containing water is adopted for chlorination, and thionyl chloride is added once without cooling, so as to speed up the process, and reduce energy consumption. The employed solvent is more conducive to release of gas products such as sulfur dioxide generated in the chlorination process and promotion of yield increase, and reduces the generation of the other salts and separation burden.

The invention relates to a silicon piezoresistive type pressure sensor chip comprising a silicon piezoresistive type pressure sensor base body, an isolation layer, a stability enhancement layer, a metal layer, contact holes, and a silicon substrate heavily-doped region. The chip is characterized in that the silicon piezoresistive type pressure sensor is made of an SOI silicon wafer; and a silicon dioxide layer is buried below piezoresistors. The isolation layer covers the silicon piezoresistive type pressure sensor base body; the contact holes are etched in the isolation layer and are filled with metals; the metals and the silicon substrate heavily-doped region are in ohmic contact and the metals are also connected with the metal layer of the chip surface; the stability enhancement layer is arranged on the isolation layer; and the stability enhancement layer and the metals in the contact holes are electrically connected by the metal layer. A highest potential point of the chip is formed at the metal layer, thereby forming a power supply welding plate of the sensor. The chip has the following advantages: on the premise that the structure of the traditional silicon piezoresistive type pressure sensor chip is not changed substantially, the structure of the silicon piezoresistive type pressure sensor chip is changed slightly and a few process steps are added, so that the output stability is improved obviously.

The invention relates to a semiconductor device in the field of power electronics, and in particular relates to a full-self-aligned insulated gate bipolar transistor device and a manufacturing method thereof. The device comprises a first conduction type substrate, and is characterized in that a second conduction type base region is formed in a first primary plane of the first conduction type substrate; and a second conduction type deep diffusion region is formed in the second conduction type base region and is in the shape of a Chinese character 'ao' meaning concave. The bipolar transistor device adopts insulated side walls and a technology of full self alignment, photolithography is not needed, the width of a polysilicon window can be reduced to 4 microns and even 2 microns, and thus more refined patterns can be achieved.

The invention discloses a semiconductor starting device based on spiral polycrystalline silicon field effect transistor charging. The semiconductor starting device is characterized in that the first end of a resistor is connected with the drain of a field effect transistor to serve as an input end, the second end of the resistor, the grid of the field effect transistor and the first end of an electronic switch are connected with the cathode of a diode, the source of the field effect transistor and the cathode signal input end of a feedback control module are connected with the first end of a capacitor to serve as an output end, the output end of the feedback control module is connected with the control input end of the electronic switch, and the anode signal input end of the feedback control module, the second end of the capacitor, the second end of the electronic switch and the anode of a voltage stabilizing diode are grounded. The invention further discloses a manufacturing process of the semiconductor starting device. The manufacturing process uses the field effect transistor integrated by a BCD process, the resistor and the voltage stabilizing diode. The semiconductor starting device has the advantages that the integrated field effect transistor is used to directly charge the capacitor, and due to the fact the integrated field effect transistor is low in resistance and power consumption when the field effect transistor is on, high power efficiency, low loss and low heating value are achieved.

The invention relates to a method for eliminating the image defect at the edge area of semi-conductor crystal chip, which is characterized in that: the invention adds the process that washing the edge of chip after the developing process that forming optical etching image; and eliminates the constriction deformation image in the edge area, to avoid the constriction deformation image being removed to cause defects on other qualified images of chip, to improve the pass percentage of product.

The invention discloses a process for manufacturing an efficient polycrystalline cell. The process includes the steps of silicon wafer surface texturing, diffusion, etching, silicon nitride thin film deposition, and printing and sintering in sequence, and is characterized in that a step of texturing through reactive ion etching is added between the silicon wafer surface texturing step and the diffusion step, a step of plating a Al2O3 film is added between the etching step and the silicon nitride thin film deposition step, the Al2O3 film is deposited on the reverse side of the silicon wafer, a laser grooving step is added between the silicon nitride thin film deposition step and the printing and sintering step, and laser grooving is performed on the Al2O3 film. The photoelectric conversion efficiency of a polycrystalline cell manufactured by application of the process provided by the invention can be improved.

The invention relates to a novel fractal PGS (Program Generation System) structure. As the existing the on-chip spiral inductor and transformer generate an alternating electromagnetic field, induced current is caused on a substrate to generate energy consumption and reduce the inductance and the Q value. The PGS is located in the central part of a coil-wound inductor/transformer, a first-order, second-order, third-order, or even higher order pattern grounded shield layer is constructed by a metal layer with a thin bottom on the basis of an H-shaped basic unit and a cross-shaped basic unit through the self-similarity of fractal theory and the iterative theory. The novel fractal PGS structure screens out the electromagnetic field which permeates the substrate effectively, reduces the induced current which is capable of generating on the substrate and the substrate surface area, achieves the substrate energy consumption and improves the function of inductance and quality factor.

The invention relates to a passivation contact solar cell and a preparation method thereof. The solar cell comprises an N-type crystalline silicon substrate, wherein the front surface of the N-type crystalline silicon substrate sequentially comprises an emitter layer, an aluminum oxide passivation layer, a silicon nitride antireflection layer and a metal slurry layer from bottom to top; wherein the back surface of the N-type crystalline silicon substrate sequentially comprises a tunneling oxide layer, a phosphorus-doped polycrystalline silicon layer, a silicon nitride antireflection layer anda metal slurry layer from bottom to top. According to the solar cell, the open-circuit voltage and the short-circuit current of the cell can be remarkably improved, so that the efficiency of an n-typepassivation contact cell can be improved; moreover, the light utilization rate can also be improved, the back surface recombination rate is reduced, the cell efficiency is improved by 0.15% or above,meanwhile, additional process steps do not need to be added, and the method is simple and suitable for mass production.

The invention discloses an error detection system for the electric energy of an electric energy meter and a detection method thereof. The system comprises a to-be-detected electric energy meter, a standard electric energy meter and a detection device, a first clock module of the to-be-detected electric energy meter is used for outputting a first current moment of the to-be-detected electric energymeter when the to-be-detected electric energy meter meters the electric energy of a preset threshold value each time, a second clock module of the standard electric energy meter is used for outputting a second current moment of the standard electric energy meter when the standard electric energy meter meters the electric energy of the preset threshold every time, and the inspection device is usedfor carrying out error detection on the to-be-detected electric energy meter according to the first current moment and the second current moment, so that the technical problem that a detection methodis more complex when the electric energy error detection is carried out on the existing electric energy meter, is solved.