The invention discloses a multilayer
composite membrane passivation structure of a table top high-
power semiconductor device. The multilayer
composite membrane passivation structure comprises P-type
boron junction areas and an N-type
phosphorus junction area, the upper end and the lower end of the N-type
phosphorus junction area are provided with the P-type
phosphorus areas respectively, and an alpha-
polycrystalline silicon layer, a semi-insulating
polycrystalline silicon thin membrane, a low-temperature heat oxidation layer, a high-temperature Si3N4
thin membrane, a
negative charge glass
passivation layer and a low-temperature heat oxidation layer are sequentially arranged on the surface of a PN junction of a table top of the table top high-
power semiconductor device from inside to outside. A
manufacturing technology of the multilayer
composite membrane passivation structure of the table top high-
power semiconductor device includes the following steps: a, depositing the alpha-
polycrystalline silicon, b, depositing semi-insulating polycrystalline
silicon, c, depositing the low-temperature heat oxidation layer, d, depositing Si3N4, e, conducting passivation on glass, and f, depositing the low-temperature heat oxidation layer in the outmost layer. The multilayer composite membrane passivation structure and the
manufacturing technology have the advantages that the alpha-polycrystalline
silicon layer is deposited, so that
crystal lattice
adaptation can be achieved, damage to
crystal lattices of a
silicon wafer in a groove can be repaired, leaked currents in the surfaces of junctions are reduced, and the stability and the reliability of the device at the high temperature are improved.