The invention discloses a method for preparing a
silicon-based high-mobility
CMOS provided with an III-V / Ge channel. The method comprises steps as follows: a
germanium layer is grown on a
silicon substrate; a low-temperature
nucleation gallium arsenide layer, a high-temperature
gallium arsenide layer, an on-growth semi-insulating InGaP (
gallium indium phosphide) layer and a
gallium arsenide cover
coating are sequentially grown on the
germanium layer after the first annealing, so that a sample is formed; the
gallium arsenide cover
coating of the sample is subjected to a
gallium arsenide polishing process, and a nMOSFET (
metal oxide semiconductor field effect transistor) structure is grown after the sample is subjected to secondary annealing; an area is selected on the surface of the nMOSFET structure for ICP (
inductively coupled plasma)
etching, downward
etching from the nMOSFET structure to the
germanium layer is performed to form a groove, and
silicon dioxide
layers are grown in the groove and on the surface of the nMOSFET structure in a PECVD (
plasma enhanced
chemical vapor deposition) manner; the area selected for
etching is subjected to ICP etching again from the
silicon dioxide layers to the germanium layer, and a groove is formed; the sample is cleaned, and a germanium nucleating layer and a germanium top layer are grown in the groove with an ultra-high vacuum
chemical vapor deposition method; the germanium top layer is polished, and a part of
silicon dioxide layers on the nMOSFET structure are removed; and the
CMOS process of source, drain and grid electrodes is performed on the nMOSFET structure and the germanium top layer, so that the preparation of the device is finished.