105results about How to "Reduce surface electric field" patented technology

The invention relates to a semiconductor device, an n-type MOS transistor and a manufacturing method thereof. The semiconductor device comprises a semiconductor substrate, a grid medium layer, a grid electrode, side walls, a light doping source / drain region, a heavy doping source / drain region, and a fluorine ion implantation region, wherein the gird medium layer, the grid electrode and the side wall are positioned inside an input / output device region of the semiconductor substrate; the low doping source / drain region and the heavy doping source / drain region are positioned inside semiconductor substrates in an n-type MOS transistor region and a p-type MOS transistor region of the input / output device region; and the fluorine ion implantation region is positioned inside a semiconductor substrate in the n-type MOS transistor region of the input / output device region. Correspondingly, the invention also provides a method for manufacturing the semiconductor device, the n-type MOS transistor and the method for manufacturing the n-type MOS transistor. The fluorine ion implantation region is formed in the low doping source / drain region of the n-type MOS transistor region, and fluorine ions inthe fluorine ion implantation region and silicon in the semiconductor substrate form fluorine-silicon groups so as to prevent the formation of charge traps, prevent the aggregation of charges in thelow doping source / drain region under the condition of additional voltage, and forming hot carrier effect.

The invention provides a semiconductor structure and a forming method thereof. The forming method comprises the steps that a semiconductor substrate is provided, and a body region is formed in the semiconductor substrate; a drift region is formed in the body region, and the doping type of the drift region is opposite to that of the body region; a channel region is formed in the body region, the part of the channel region extends in the direction where the drift region is located to form at least one channel extension region, the channel extension regions and the drift region are distributed inan interdigital shape, and the doping type of the channel region is identical to that of the body region; an isolation region is formed in the drift region, and the end portions of the channel extension regions are located below the isolation region; a grid structure is formed on the surface of the semiconductor substrate; a source region is formed in the channel region at one side of the grid structure, and a drain region is formed in the drift region and located at the side, away from the channel region, of the isolation region.