Shallow-groove isolation structure transverse semiconductor device arranged in staggered and interdigital way

Abstract

A shallow-groove isolation structure transverse semiconductor device arranged in a staggered and interdigital way comprises a P-type substrate, wherein a high-voltage N-type region is arranged on theP-type substrate, an N-type drift region and a P-type body region are arranged on the high-voltage N-type region, an N-type drain region and three shallow-groove isolation regions are arranged in theN-type drift region, an N-type source region and a P-type region are arranged in the P-type body region, a U-shaped gate oxide layer is further arranged on the high-voltage N-type region, a U-shaped opening of the gate oxide layer faces a drain end, two ends of the gate oxide layer respectively extend to a part above the P-type body region and a part above the shallow-groove isolation regions, a poly-silicon gate field plate is arranged on the gate oxide layer, drain metal contact, source metal contact and body region metal contact are respectively arranged on upper surfaces of the N-type drain region, the N-type source region and the P-type region, and the shallow-groove isolation structure transverse semiconductor device is characterized in that the shallow-groove isolation regions are arranged in the drift region in the staggered and interdigital way. By the structure, relatively low conduction resistance can be obtained on the basis that the breakdown voltage is not changed.

Description

technical field [0001] The invention relates to the field of power semiconductor devices, and relates to a lateral semiconductor device with an interdigitated shallow trench isolation structure. Background technique [0002] Lateral Double-Diffused MOSFET (LDMOS) has the advantages of high breakdown voltage, high input impedance and easy integration with other devices, and is widely used in high-voltage integrated circuits and power integrated circuits . Compared with traditional MOSFET devices, LDMOS devices have a low-doped drift region. When a high voltage is applied between the drain and source, the drift region is completely depleted, so it can withstand a higher voltage. [0003] In the design of the LDMOS device structure, shallow trench isolation technology (Shallow Trench Isolation, STI) is often used in the drift region to improve the withstand voltage capability of the device. For LDMOS devices with STI structure, STI can bear most of the electric field in the d...

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Problems solved by technology

Although this process can improve the withstand voltage capability of the device, the STI structure will increase the flow path of the current from the source to the drain, resulting in an increase in the on-resistance of the device.

Therefore, when the STI structure is used in the drift region of LDMOS, a better compromise between breakdown voltage and on-resistance cannot be achieved.

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