59 results about "Surface capping" patented technology

The invention provides a shell, method for manufacturing the shell and mould for manufacturing the shell. The shell comprises a film, a base body and a display window. The film is covered on the surface of base body and the display window, which are made of different materials, disposed in one plane and connects with each other.The integral molding process of film, base body and display window for the shell is as follows: placing film in cavity of mould, molding the base body and the display window which are separately binding with the film, pressing display window in mould by compression mechanism of mould, then shell is obtained and taken out. The invention can accomplish seamless bond for base body and display window, stable binding quality, and high production efficiency; shell quality is promoted by covering film on base body and display window to smooth shell and compressing in mold for obtaining smooth display window.

The invention relates to a silicon nano-wire, in particular to a method for preparing a two-sided silicon nano-wire array. According to the method, a silicon surface is etched by combining the corrosivity of a solution and the catalysis of metal ions at low temperature to form the silicon nano-wire array. The method comprises the following steps of: cleaning the silicon surface; passivating the surface of a silicon wafer by using hydrogen; covering a uniform layer of silver nanoparticle network on each of two surfaces of the silicon wafer by using a chemical plating method; preparing the two-sided silicon nano-wire array; and removing excessive silver nanoparticles. The method has the advantages that: expensive equipment and high-temperature environment are avoided in the preparation process, and the method is easy to operate and control, low in cost and high in efficiency, and can be applied to large-scale industrial production.

We have discovered a method of improving step coverage of a copper seed layer deposited over a semiconductor feature surface which is particularly useful for small size features having a high aspect ratio. Using a contact via as an example of a high aspect ratio feature, we have demonstrated that despite previously-held views, it is possible to increase the copper seed layer coverage simultaneously at the bottom of the via and on the wall of the via by increasing the percentage of the depositing copper species which are ions. The percentage of species ionization which is necessary to obtain sufficient step coverage for the copper seed layer is a function of the aspect ratio of the feature. For features having a 0.25 mum or smaller feature size, an aspect ratio of about 3:1 requires that about 50% or more of the copper species be ions at the time of deposition on the substrate. As the aspect ratio increases to about 4:1, the percentage of species which are ions is preferably increased to between about 60% and 70%. When the aspect ratio is about 5:1 or greater, the percentage of species which are ions is preferably increased to greater than 80%. This increase in the percentage of copper species which are ionized can be achieved using techniques known in the art, such as, for example, laser ablation of the copper target, electron cyclotron resonance, hollow cathode, and applicants' preferred technique, an inductively coupled RF ion metal plasma. We have further discovered that when an inductively coupled plasma is used to increase ionization, an increase in power to the ionization source is not enough to obtain the desired percentage of ions in many cases. It is also necessary to increase the plasma gas pressure. Typically the plasma gas is argon, and the argon pressure in the copper seed layer deposition chamber is increased to fall within the range of about 20 to about 100 mT, preferably between about 30 mT and 70 mT.

A method for fabricating a semiconductor device structure includes applying a stress buffer material onto a semiconductor device structure and spreading the stress buffer material. When the stress buffer material is spread, it substantially fills recesses formed in a surface of the semiconductor device structure and imparts the stress buffer material with a substantially planar surface. The thickness of the stress buffer material covering the surface of the semiconductor device structure may be less than the depths of the recesses. The surface may remain substantially uncovered by the material.

The present invention is directed to a non-contact, single-component developing system for electrophotographic machines that effectively reduces the impact of adhesion forces on the development process. The developing system of the present invention utilizes a single-component toner that tends to reduce the adhesion forces that hold the toner particles on a toner support member. Preferably, the toner is combined with large and small silica particles having a concentration by weight that results in an optimum surface coverage of toner particles by large and small silica particles that facilitates a reduction in the adhesion forces holding the toner particles on the toner support member.