48results about How to "Stable breakdown voltage" patented technology

The invention discloses a 4H-SiC metal-semiconductor field effect transistor with a double-sunken buffer layer. The 4H-SiC metal-semiconductor field effect transistor comprises a 4H-SiC semi-insulating substrate, a P type buffer layer and an N type channel layer from bottom to top, wherein a source electrode cap layer and a drain electrode cap layer are respectively arranged on two sides of the N type channel layer; a source electrode and a drain electrode are respectively arranged on the surfaces of the source electrode cap layer and the drain electrode cap layer; a gate electrode is formed on one side, close to the source electrode cap layer, above a channel; grooves are arranged on the upper end face of the P type buffer layer and under a gate source and a gate leakage. The 4H-SiC metal-semiconductor field effect transistor has the advantages that the output drain electrode current is obviously improved, and the breakdown voltage is stable.

The invention discloses a 4H-SiC metal semiconductor field effect transistor and a manufacturing method thereof. The field effect transistor comprises a 4H-silicon carbide SiC semi-insulating substrate, a P-type buffer layer and an N-type channel layer, wherein the P-type buffer layer covers the 4H-silicon carbide SiC semi-insulating substrate; the N-type channel layer covers the P-type buffer layer and comprises a first N-type channel region, a second N-type channel region and a third N-type channel region; the second N-type channel region is formed between the first N-type channel region and the second N-type channel region; a source cap layer and a drain cap layer are formed on two sides of the surface of the N-type channel layer; a source is formed on the surface of the source cap layer; a drain is formed on the surface of the drain cap layer; and a gate electrode is formed on the N-type channel layer and close to the source cap layer. According to the 4H-SiC metal semiconductor field effect transistor, the technical problems that the existing 4H-SiC metal semiconductor field effect transistor is unstable in current and low in breakdown voltage are solved.

The invention is suitable for the field of semiconductors, and provides a method for preparing an ohmic contact electrode of a GaN-base device. The method comprises the following steps: growing a first dielectric layer on the upper surface of a device; injecting silicon ions and/or indium ions in a region, corresponding to an ohmic contact electrode region, of the first dielectric layer and the ohmic contact electrode region of the device; growing a second dielectric layer on the upper surface of the first dielectric layer; activating the silicon ions and/or the indium ions by a high-temperature annealing process, and forming N-type heavy doping; respectively removing the parts, corresponding to the ohmic contact electrode region, of the first dielectric layer and the second dielectric layer; growing a metal layer on the upper surface of the ohmic contact electrode region of the device, and forming the ohmic contact electrode. The prepared ohmic contact electrode can guarantee the flatsurface of the metal layer and the smooth and aligned edges, is stable in breakdown voltage of the device, is high in reliability, and is long in service life.

The invention discloses a power device with a fixed interface charge field limitation ring. The power device comprises a field oxide layer and an active layer, wherein the field oxide layer is arranged on the active layer, at least one fixed interface charge region is arranged in the field oxide layer, and the fixed interface charge region is arranged at a lower part of the field oxide layer and is in contact with a lower surface of the field oxide layer, namely an interface surface of the field oxide layer and the active layer. By the power device, the problems of breakdown voltage drop and device failure caused by impurity diffusion in an FLR region of an existing power device can be solved, the breakdown voltage of the device is effectively improved, the electric field distribution of a surface of the active layer is improved, and the electric field distribution is more uniform.

The invention provides a Zener diode manufacturing method based on a CMOS manufacturing process. A polysilicon deposition process, a Zener implanting process, a sidewall dielectric layer deposition process, a sidewall dielectric layer etching process and a source/drain implanting process are successively performed. The traditional Zener implanting process is performed before the sidewall dielectric layer deposition process, the sidewall dielectric layer etching process and the source/drain implanting process, thereby preventing substrate damage by the sidewall dielectric layer etching process and substrate damage in formation of amorphous structures which may caused by the source/drain implanting process, so that concentration distribution uniformity of impurities which are implanted into the Zener diode is improved, thereby obtaining a stable breakdown voltage in breakdown of the Zener diode, preventing defects of large leakage current and low uniformity of the leakage current before breakdown of the Zener diode, and improving market competitiveness of the product.

The invention provides a voltage-resistant terminal ring structure and a power device. The voltage-resistant terminal ring structure comprises a substrate, multiple field rings, multiple field plates, dielectric films and at least one additional ion injection area; the field rings are arranged on the portion, close to a second surface, in the substrate at intervals, the conduction type of the field rings is opposite to that of the substrate, the field rings comprise at least one voltage-resistant ring and two equipotential rings, and the two equipotential rings are sequentially arranged in the direction far away from the voltage-resistant rings; the field plates and the field rings are arranged in a one-to-one corresponding mode, parallel segments corresponding to the voltage-resistant rings extend in the direction close to a third surface, and parallel segments corresponding to the equipotential rings extend in the direction far away from the third surface; the dielectric films are arranged on a second part surface and part of a first part surface; the additional ion injection areas are arranged on the portions, between the adjacent voltage-resistant rings and equipotential rings, of the substrate, and the conduction type of the additional ion injection areas is opposite to that of the substrate. The reverse breakdown voltage of the power device with the structure is stable.

The invention provides a power device with a surface charge region structure, and the power device comprises a P substrate I (1), a floating equipotential layer (4), a P substrate II (2) and a drift region (5), wherein the P substrate I (1), the floating equipotential layer (4), the P substrate II (2) and the drift region (5) are arranged in order from the bottom to the top. The drift region (5) is provided with an N+ drain region, a drain electrode (10), a gate electrode (12), a source electrode (11), an N+ contact region, a P well (7), and a P+ source region. A series of laterally and equidistantly distributed N+ charge regions (6) are disposed at the top of the drift region (5) and within the drift region to form the surface charge region. Because the surface of the drift region is provided with a surface charge region structure of a series of equidistantly distributed N+ charge regions, the surface charge region generates interface charges, and the electric field in the charge region is improved, and the lateral withstand voltage of the device is improved. The interface charge improves the longitudinal electric field and longitudinal withstand voltage of a buried layer at the same time, reduces the electric field nearby the drain electrode and prevents the surface of the device from being broken down too early. Because the power device employs the surface charge region structure of equidistantly distributed N+ charge regions, the power device is simple and feasible in technology, is better in technological tolerance, and is compatible with the conventional CMOS technology.

According to an embodiment of the present invention, in a power semiconductor device comprising an active battery and an edge cell formed adjacent to the active battery for stabilizing the electric field,the active battery comprising: an N + substrate formed on an upper side of the second electrode; an N-drift layer formed on the upper side of the N + substrate; a P-base region formed on an upper portion of the N-drift layer; and a first electrode formed on an upper side of the P-base region for receiving a signal; the edge battery comprising: a field plate extending from the first electrode as a conductor; a buffer ring formed underneath the field plate by injecting the first impurity ions above the N-Drift layer extending from the active battery; a plurality of field loops having a predetermined horizontal gap and width from the buffer ring formed by injecting the first impurity ions over the N-drift layer; and a field effect oxide film formed between the field plate and the buffer ring and covering a plurality of field loops.

The present invention discloses a power device having an interface charge trench high-voltage interconnection structure capable of generating interface charges, enhancing a surface transverse electricfield and improving a surface horizontal withstand voltage. The power device comprises a drift region, a buried layer 1 and a substrate which are arranged from top to bottom in order; a buried layer2 is arranged above the drift region, and a surface structure is arranged above the buried layer 2; and the buried layer 2 is provided with medium grooves 2 extending into the drift region, and the medium grooves 2 are uniformly distributed in a transverse direction. The breakdown voltage of the power device provided by the invention can reach 427V, a traditional groove-gate structure breakdown voltage is 258V, and the breakdown voltage is increased by 65.5%. The power device is uniform in equipotential line distribution, a charge shielding effect allows the surface high voltage to reduce theeffect on the drift region, and therefore, the concentration of the drift region is greatly improved, the resistance is reduced, and the breakdown voltage is increased.